IC Compiler II: Block-level Implementation

Overview

Learn to use IC Compiler II to run a complete place and route flow on block-level designs. The flow covered within the workshop addresses the main design closure steps for multi-voltage designs, with multi-corner multi-mode (MCMM) timing and power challenges. All topics are accompanied by very engaging hands-on lab exercises.

Day 1 topics include: ICC II GUI usage; objects, blocks and application options; block-level floorplanning; placement and incremental post-placement optimizations.

Day 2 topics include: Library preparation for IC Compiler II NDM cell libraries; IC Compiler II's re-architected multi-corner/mode/scenario design setup process; classic clock tree synthesis as well as "concurrent clock-and-data" optimization.

Day 3 topics include: More details on CTS setup; signal routing and post-route optimization; top-level integration and implementation using block abstracts; functional and timing ECOs, signoff DRC and metal filling using IC Validator.

Objectives

At the end of this workshop you should be able to use IC Compiler II to:

Use the GUI to analyze the layout during the various design phases
Control object and layer visibility, rearrange the GUI to suit your needs
Perform timing analysis using the GUI
Describe what elements an NDM cell library contains, and create an NDM technology-only library
Create a block-level floorplan including automatic voltage area shaping and placement, automatic macro placement and advanced connectivity analysis, intro to pattern-based power network synthesis, macro keepouts and placement blockages, and congestion map analysis
Perform and debug design setup to create an initial design which is ready for placement; this includes loading the netlist, floorplan- and scan-DEF files; Loading multi-voltage design data: UPF and voltage-area definitions; creating an NDM design library, and applying common timing and optimization controls
Create modes, corners and scenarios for IC Compiler II’s rearchitected MCMM environment
Use timing derate as well as AOCV and POCV derating
Perform concurrent MCMM standard cell placement and related optimizations to minimize timing violations, congestion, and power; includes Design Fusion setup, leakage, dynamic and total power set up, layer optimization, spare cell handling, multibit register banking, placement attractions, congestion-driven restructuring, route driving extraction (RDE), as well as embedded ICG optimization.
Perform setup for clock tree synthesis and data-path optimization (define exceptions, targets, non-default routing rules, etc.)
Execute the "classic" CTS and optimization flow, or the concurrent clock-and-data (CCD) flow; global and local skew optimization is covered
Analyze clock tree and timing results post-CTS using the GUI and text reports
Perform routing setup to control DRC fixing, via optimization, antenna fixing, and crosstalk reduction
Perform automated via ladder insertion for EM and performance optimization
Route critical, secondary PG and signal nets and perform post-route optimization including post-CTS, CCD, power and crosstalk optimization
Perform PrimeTime and StarRC based timing analysis and optimization within IC Compiler II
Use ECO Fusion to perform timing ECO loops controlled from within IC Compiler II
Create block abstracts and frame views for top-level assembly and implementation
Analyze and fix physical DRC violations, using IC Validator from within IC Compiler II (In-Design Flow)
Insert standard cell metal fillers and perform metal filling using IC Validator
Perform functional unconstrained and freeze-silicon ECOs
Generate all required output files for signoff extraction and static timing analysis in PrimeTime-SI
Perform timing ECOs in combination with Primetime Physical Guidance using ECO Fusion

Audience Profile

ASIC, back-end, or layout designers who will be using IC Compiler II to perform placement, CTS, and routing on block-level designs

Prerequisites

While prior knowledge of IC Compiler II or IC Compiler is not needed, knowledge of general (non-tool specific) standard cell-based placement, CTS, and routing concepts and terms is helpful.

An understanding of basic digital ASIC design concepts is assumed, including: