General Training (optional)

This general training is pre-requisite for purple certification program. Users are expected to be proficient with basic programing: Linux, TCL/TK, Perl, and Python. This course will provide some useful links for users to gain the required knowledge. Users are welcome to utilize any similar trainings available at their disposal online.

VLSI Fundamentals & ASIC Design Flow (Test Out - Optional)

The following 5 courses are prerequisites. If you think you have the knowledge, you may take the exam and test out. Passing the exam will give you completion status for the respective course. 

CMOS Fundamentals: This course will provide physics of semiconductors and its electrical properties including basics of CMOS device fabrication process and its enhancements for advanced devices.​​​​​​​

VLSI Basics: This course will cover the basics of digital design, CMOS circuit representation using HDL models, re-convergent models, stick diagrams, logic synthesis, technology library, VLSI design timing parameters, physical synthesis, and an introduction to FPGA design.  

Digital Design Fundamentals: This course will cover refreshing number system and Boolean algebra, logic optimization using Karnaugh Maps, canonical forms of logic representation, basics of Graph theory, logic optimization by design techniques and more.

Very Deep Sub Micron (VDSM):  This course will cover dealing with the challenges and ways to address very deep submicron designs such as technology trends, speed and performance trends of VLSI design, high speed challenges, interconnect challenges, process challenges of VDSM processes and ways to address each challenge.

ASIC Design Flow: This introductory course will explain ASIC design concepts and flow, technology Libraries and their relevance in VLSI design​, and how to constrain the ASIC design to meet design goals​. Topics covered include design verification, design synthesis, design for testability, design implementation and signoff.

Duration: 5 weeks

Test Out Exam Details: Each of the above courses has an equivalent exam that can be taken first to gauge how well you know the content. Answer 50 questions in 90 minutes and achieve an 85% or higher score to pass the exam and get awarded a badge. 

Physical Design Track

This 12-week track (includes prerequisites) comes with everything you need to know about Physical Design and gives you hands-on experience with Synopsys tools. 

Physical Design I: Foundation - This introduction training to physical design covers creation of physical library and its characterization data and ends with introduction to physical design RTL to GDS II flow — modeling abstraction, timing, signal integrity, low power, UPF, DFT, library preparation, library creation and setting constraints.

Physical Design II: Comprehensive - In this course, you will get introduced and trained on Synopsys physical design from learning in-depth usage of Fusion Compiler and IC Compiler II Graphic User Interface, Floorplanning, IO Placement and Routing, Clock Tree Synthesis and its flows, routing with post route optimization and signal EM fixing. You will also learn verification for DRC and LVS with ECO changes and its features. Course includes live demos of features and examples using Synopsys tools. The course will end with Advance Node Impact and features in Synopsys Physical Design Flow and tools.

Physical Design III: Jumpstart with Synopsys Tools - 

• Fusion Compiler: Synthesis and Design Implementation Jumpstart-  Jumpstart into Fusion Compiler implementation methodology. You will learn to use Fusion Compiler to perform complete physical synthesis, which is the unification of traditional synthesis and IC Compiler II placement functionality.
  
• PrimeTime: Jumpstart- Get an overview of the main capabilities of PrimeTime, the timing analysis flow and the different inputs required to perform the timing analysis. 
  
• StarRC: Jumpstart- StarRC jumpstart training covers the basics of performing Parasitic Extraction using the StarRC Tool.
  

Fusion Compiler: Design Creation and Synthesis- Foundation training for Design Creation and Synthesis using the Synopsys Fusion Compiler™ tool. This includes GUI usage, creating design library, reading and managing RTL, applying power intent, floor planning, performing MCMM setup, configuring CCD optimization, configuring power optimization, and employing techniques to improve timing and congestion. Virtual labs provided for this course. When ready, follow instructions in the course to request for lab access.

Fusion Compiler: Design Creation and Synthesis Exam- Take this exam to demonstrate the knowledge acquired from design creation and synthesis course. Pass the exam and recieve a digital Badge. 

Fusion Compiler: Design Implementation- Foundation training for Design Implementation with Fusion Compiler flow includes executing clock tree synthesis (CTS) or the concurrent clock-and-data (CCD) flow, analyzing the clock tree, running post-CTS global route-based optimization, specifying timing and DRC constraints, performing routing setup and routing, and optimizing the post-route design. Virtual labs provided for this course. When ready, follow instructions in the course to request for lab access.

Fusion Compiler: Design Implementation Exam-  Take this exam to demonstrate the knowledge acquired from design implementation course. Pass the exam and receive a digital badge.

Duration: 12 weeks (includes 5 weeks for pre-requisites)

Cost: $2100 USD

Exam Details: Answer 50 questions in 90 minutes and achieve an 85% or higher score to pass the exam and get awarded a badge for each exam.

Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Physical Design Learning Path completion certificate and a digital badge.