This 12-week track comes with everything you need to know about Design for Testability (DFT) in the ASIC design flow. It covers the need for test, fault modeling, test insertion methods, automatic test pattern generation (ATPG), concept of test coverage, and advanced test techniques.
Design For Test I: Foundation - This introduction covers DFT, including testing of ICs, wafer sorting, defect-fault mapping, fault modeling, fault simulation, concept of DFT testability, ATPG generation, and advanced test techniques.
Design For Test II: Comprehensive - In this course, you will learn about how to use DFT with Synopsys TestMAX™ Advisor, scan the design flow with DFT and Diagnosis, fault simulation, and test insertion using TestMAX DFT
Design For Test III- Jumpstart with Synopsys Tools
- TestMAX DFT: Jumpstart - You will learn to use TestMAX DFT to perform gate-level DFT rule checks, fix DFT DRC rule violations, insert scan using top-down and bottom-up flows, and export the results to downstream tools.
- TestMAX Manager: Jumpstart - Get an overview of the TestMAX Manager flow for generating and instantiating DFT IP, such as DFTMAX Scan Compression, On-Chip Clock Controller, etc. into a user RTL.
- TestMAX SMS: Jumpstart - Memories are complex and well structured. Testing memories involves an in-depth understanding of their function both logically and physically. Each memory has a different configuration and the test mechanism used to test the memory needs to be customized as per its architecture. Learn about how to address this requirement using Synopsys’ TestMAX Star Memory System (SMS) In this training, we will briefly discuss the SMS architecture for different memory configurations and accessing these memories from the SOC level.
TestMAX DFT – Learn in depth how to use Synopsys TestMAX™ DFT to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. Explore essential techniques to support large, multimillion gate SoC designs including the bottom-up scan insertion flow in the logical (Design Compiler®) domain.
TestMAX DFT Exam - This exam enables you to demonstrate the knowledge required to use TestMAX™ DFT for DFT rule checks and scan insertions in SoC designs.
TestMAX Advisor – Learn to use Synopsys TestMAX™ Advisor (previously known as SpyGlass® DFT) to perform RTL testability analysis that allows you to fine-tune your RTL early in the design cycle. This enables you to verify the design scan readiness and test robustness and work toward meeting fault and test coverage goals.
TestMAX Advisor Exam - This exam enables you to demonstrate the knowledge required to use TestMAX Advisor for RTL testability analysis and design scan readiness.
TestMAX ATPG - You will learn how to use TestMAX ATPG to generate test patterns for stuck-at faults given a scan gate-level design created by TestMAX DFT or other tools, and describe the test protocol and test pattern timing using STIL.
TestMAX ATPG Exam – This exam enables you to demonstrate the knowledge required to use TestMAX ATPG to generate test patterns for stuck-at faults in SoC designs.
Fusion Compiler: DFT Synthesis - In this course, you will learn about using Fusion Compiler to perform Scan Synthesis. Course starts with fundamentals of Scan testing, the supported Scan synthesis flows in Fusion Compiler, running and debugging Design Rule Checks, and then proceeds to building scan chains at the block-level.
Fusion Compiler: DFT Synthesis Exam: This exam enables you to demonstrate the knowledge required to use Fusion Compiler with DFT synthesis for DRC checks and building scan chains for the design.
Duration: 12 weeks (includes 5 weeks for prerequisites)
Cost: $2100 USD
Exam Details: Answer 25-50 questions in 60-90 minutes and achieve an 85% or higher score to pass the exam and get awarded with a badge for each exam.
Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Purple Certification: DFT Learning Path completion certificate and a digital badge.