Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Accelerated Customer Education is proud to offer a Purple Certification Program for Engineering students currently in their final year of studies, fresh graduates or new hires. This comprehensive program gives exposure to all things today’s engineers need to kick start their career as Design Engineers, Signoff Engineers, Test Engineers or Verification Engineers. Choose one of the 5 tracks; Physical Design, Design Verification, RTL Synthesis, Design for Test and Analog Mixed Signal Circuit and Layout Design.
Registration Now Open for the Physical Design and RTL Synthesis Tracks
All tracks require the completion or test out of the Pre-Requisite Courses prior to the track specific courses.
General Training (optional)
This general training is pre-requisite for purple certification program. Users are expected to be proficient with basic programing: Linux, TCL/TK, Perl, and Python. This course will provide some useful links for users to gain the required knowledge. Users are welcome to utilize any similar trainings available at their disposal online.
VLSI Fundamentals & ASIC Design Flow (Test Out - Optional)
The following 5 courses are prerequisites. If you think you have the knowledge, you may take the exam and test out. Passing the exam will give you completion status for the respective course.
CMOS Fundamentals: This course will provide physics of semiconductors and its electrical properties including basics of CMOS device fabrication process and its enhancements for advanced devices.
VLSI Basics: This course will cover the basics of digital design, CMOS circuit representation using HDL models, re-convergent models, stick diagrams, logic synthesis, technology library, VLSI design timing parameters, physical synthesis, and an introduction to FPGA design.
Digital Design Fundamentals: This course will cover refreshing number system and Boolean algebra, logic optimization using Karnaugh Maps, canonical forms of logic representation, basics of Graph theory, logic optimization by design techniques and more.
Very Deep Sub Micron (VDSM): This course will cover dealing with the challenges and ways to address very deep submicron designs such as technology trends, speed and performance trends of VLSI design, high speed challenges, interconnect challenges, process challenges of VDSM processes and ways to address each challenge.
ASIC Design Flow: This introductory course will explain ASIC design concepts and flow, technology Libraries and their relevance in VLSI design, and how to constrain the ASIC design to meet design goals. Topics covered include design verification, design synthesis, design for testability, design implementation and signoff.
Duration: 5 weeks
Test Out Exam Details: Each of the above courses has an equivalent exam that can be taken first to gauge how well you know the content. Answer 50 questions in 90 minutes and achieve an 85% or higher score to pass the exam and get awarded a badge.
Physical Design Track
This 12-week track (includes prerequisites) comes with everything you need to know about Physical Design and gives you hands-on experience with Synopsys tools.
Physical Design I: Foundation - This introduction training to physical design covers creation of physical library and its characterization data and ends with introduction to physical design RTL to GDS II flow — modeling abstraction, timing, signal integrity, low power, UPF, DFT, library preparation, library creation and setting constraints.
Physical Design II: Comprehensive - In this course, you will get introduced and trained on Synopsys physical design from learning in-depth usage of Fusion Compiler and IC Compiler II Graphic User Interface, Floorplanning, IO Placement and Routing, Clock Tree Synthesis and its flows, routing with post route optimization and signal EM fixing. You will also learn verification for DRC and LVS with ECO changes and its features. Course includes live demos of features and examples using Synopsys tools. The course will end with Advance Node Impact and features in Synopsys Physical Design Flow and tools.
Physical Design III: Jumpstart with Synopsys Tools -
Fusion Compiler: Design Creation and Synthesis- Foundation training for Design Creation and Synthesis using the Synopsys Fusion Compiler™ tool. This includes GUI usage, creating design library, reading and managing RTL, applying power intent, floor planning, performing MCMM setup, configuring CCD optimization, configuring power optimization, and employing techniques to improve timing and congestion. Virtual labs provided for this course. When ready, follow instructions in the course to request for lab access.
Fusion Compiler: Design Creation and Synthesis Exam- Take this exam to demonstrate the knowledge acquired from design creation and synthesis course. Pass the exam and recieve a digital Badge.
Fusion Compiler: Design Implementation- Foundation training for Design Implementation with Fusion Compiler flow includes executing clock tree synthesis (CTS) or the concurrent clock-and-data (CCD) flow, analyzing the clock tree, running post-CTS global route-based optimization, specifying timing and DRC constraints, performing routing setup and routing, and optimizing the post-route design. Virtual labs provided for this course. When ready, follow instructions in the course to request for lab access.
Fusion Compiler: Design Implementation Exam- Take this exam to demonstrate the knowledge acquired from design implementation course. Pass the exam and receive a digital badge.
Duration: 12 weeks (includes 5 weeks for pre-requisites)
Cost: $2100 USD
Exam Details: Answer 50 questions in 90 minutes and achieve an 85% or higher score to pass the exam and get awarded a badge for each exam.
Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Physical Design Learning Path completion certificate and a digital badge.
RTL Synthesis Track
This 12-week track comes with everything you need to know about RTL Synthesis and gives you hands-on experience with Synopsys tools like Design Compiler NXT, Formality, and Fusion Compiler.
RTL Synthesis I: Foundation - This introduction covers the hardware description languages Verilog/VHDL and SystemVerilog used to model ASIC designs.
RTL Synthesis II: Comprehensive - In this course you will learn the RTL synthesis flow, specifically when using Design Compiler NXT in topographical mode. You will learn how to synthesize a block-level RTL design to generate a final gate-level netlist with acceptable post placement timing and congestion. The course will teach Synopsys recommended methodologies for different synthesis optimization techniques and constraining the design.
Design Compiler NXT: Foundation Exam - Take this exam to demonstrate the knowledge acquired from design creation and synthesis course.
Formality - In this course you will apply a formal verification flow for design verification and debugging of failed design. You will apply an extended flow to optimize Formality for common hardware design transformations. Increase debugging capability through techniques such as pattern analysis and maximize the verification performance.
UPF Fundamentals - This course will provide an overview and benefits of different power-saving techniques that can be achieved through UPF, highlighting areas of concern when adopting these techniques that could impact your implementation and verification schedule. The course will go through the caveats of UPF power domain creation, covering the concepts of 'good power design partitioning' to achieve optimal results. Top-down and hierarchical approaches to power domain creation are covered as well as the link between the conceptual UPF power domain definition and how that tie into the physical flow. The concepts of "supply net" and "supply set" are touched upon, covering levels of abstraction that each individual construct offers, providing SoC-based or IP-based engineers with a mechanism to implement and verify the power domain architecture of choice.
UPF Fundamentals Exam - Take this exam to demonstrate the knowledge acquired from UPF fundamentals course.
Design Compiler NXT: Clock Gating Low Power - This is an advanced course on Design Compiler NXT and will teach you how to properly set up the tool for doing power analysis by applying switching activity and to perform power optimizations technologies such as clock gating, self-gating, multibit register banking, low power placement and DesignWare minPower.
Design Compiler NXT: Clock Gating Low Power Exam - Take this exam to demonstrate the knowledge acquired from Design Compiler Low Power course.
Duration: 12 weeks (includes 5 weeks for prerequisites)
Cost: $2100 USD
Exam Details: Answer 25-50 questions in 60-90 minutes and achieve an 85% or higher score to pass the exam and get awarded a badge for each exam.
Completion Certificate: Upon completion of all the courses in this learning path including the prerequisites, you will be awarded a Purple Certification: RTL Synthesis Learning Path completion certificate and a digital badge.
All sessions are limited to 30 students. All Instructor-Led sessions will take place from 8:00 AM - 12:00 PM local time. Weekly Q&A sessions (virtual, local time) will be facilitated for Self-Paced Learning. Details will be sent upon registration.
RTL Synthesis Session 1 : August 7th - October 27th (Virtual, Pacific Time) - Hybrid $2100 USD
RTL Synthesis Session 2 : September 11th - December 1st (Virtual, Pacific Time) - Hybrid $2100 USD
Physical Design Session 1 : May 1st - July 21st (Virtual, Pacific Time) - Hybrid $2100 USD - FULL
Physical Design Session 2 : June 26th - September 15th (Virtual, Pacific Time, CA) - Hybrid $2100 USD
RTL Synthesis Session 1 : July 10th - September 29th (In-Person, Bangalore) - Hybrid $2100 USD
RTL Synthesis Session 2 : September 4th - November 24th (Virtual, India Standard Time) - Hybrid $2100 USD
Physical Design Session: June 12th - August 31st (Virtual, India Standard Time) - Hybrid $2100 USD