Cloud native EDA tools & pre-optimized hardware platforms
By James Chuang, February 11, 2021
Today, performance, power and area (PPA) targets are pre-defined values driven by multiple static metrics, including clock and data path timing, power consumption at specific voltage levels and floorplan sizes and shapes. These metrics then drive technology library characterization, design optimization and signoff closure.
Aggressive PPA goals of advanced node designs, especially high-performance computing (HPC) designs, constantly push the envelope to unlock additional PPA opportunities. If you have an advanced node design in your future, read on to see how Synopsys has you covered for advanced node signoff with Fusion Compiler™ and PrimeShield.
Both power and performance metrics are evolving to consider a much broader range of variables for advanced nodes. Let’s examine this phenomenon to understand why.
Dynamic or switching power has become a top focus for power optimization, especially for advanced node HPC applications. While lowering the operating voltage can directly reduce dynamic power, operating voltage has long been a static metric in design flows. The higher cell and power density at advanced nodes also makes any reduction to voltage supply levels an extremely difficult task. Despite this, lower voltage levels can be essential to achieve competitive performance-per-watt goals. So, a new PPA opportunity has emerged for power.
In the case of timing, proven approaches use static timing analysis (STA) to analyze each timing path and check them individually against the frequency metric. Due to the significant variability of advanced nodes, especially at low voltages, analysis of potential performance bottlenecks caused by high variability is highly desired. Statistical analysis that identifies these bottlenecks through statistical correlation of all critical paths can avoid over-compensation while improving design PPA metrics. So, a new PPA opportunity has emerged for timing performance as well.
In 2017, PrimeTime established a foundry-certified Advanced Voltage Scaling technology that enabled designers to perform accurate analysis at any voltage level within a broad range. Designers now had a way to “sweep” the voltage range, trial run the same design at various voltage levels, and eventually, find a voltage sweet-spot for the desired PPA or performance-per-watt targets. While the PrimeTime solution proved to be both accurate and effective, the sweeping process was high time and resource consuming.
Fast-forward to today, driven by strong customer demand, PrimeShield has expanded on the PrimeTime core technology and introduced a new PPA signoff analysis type called Voltage Slack which represents the minimum voltage per-cell or per-path for a design to meet performance requirements. This signoff analysis enables designers to efficiently pinpoint voltage bottlenecks to improve IR-drop robustness, drive voltage margining uniformity and uncover opportunities to fine-tune operating voltages directly.
Variable voltage is now available as a PPA optimization metric.
PrimeShield also has an innovative fast statistical engine that leverages the core engine of PrimeTime signoff. Accelerated by machine learning technology, the PrimeShield solution performs fast Monte Carlo statistical simulation on critical timing paths within minutes versus days or weeks required by traditional statistical simulations.
Its patented design variation analysis with statistical correlation modeling enables analysis and optimization on large-scale SoCs with billions of cells, an analysis was previously feasible only for a few dozen cells. The runtime challenges that prohibited full statistical design variation are gone, enabling analysis and optimization for every design of any size.
Statistical performance bottleneck analysis is now available as a PPA optimization metric.