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Achieve Your Simply Better PPA

Fusion Compiler features a unique RTL-to-GDSII architecture that enables customers to reimagine what is possible from their designs and take the fast path to achieving maximum differentiation. It delivers superior levels of power, performance and area out-of-the-box, along with industry-best turnaround time. Learn more about Fusion Compiler.

Design Success with Foundation IP & Fusion Compiler

When is 1+1 greater than 2? When using DesignWare Foundation IP & Fusion Compiler! Join Raymond and Yung in their discussion of a customer that benefited from the combination of Fusion Compiler’s machine learning and Foundation IP cells and macros. 

What Our Customers Say

Renesas: Superior Reliabilty for Automotive Designs

Arm: Enabling Arm’s Highest-Performance CPU-Core Design

Samsung: Fusion Compiler Deployment - The Journey So Far

Arm

- Jeff Kehl
Vice President of CPU Engineering, Central Engineering 

" Our collaboration with Synopsys and the deployment of Fusion Compiler delivers accelerated access to this highly optimized technology, enabling our mutual customers to design and deploy market-shaping solutions into the fast-expanding hyperscale space.. " Read more

AMD

- Mark Papermaster
CTO & Executive Vice President Technology and Engineering, AMD 

" Synopsys' Fusion Compiler helped us meet our performance and time-to-market goals for our latest products. As a result, we plan to use Fusion Compiler for the development of our next-generation products. " Read more

Broadcom

- Yuan Xing Lee
Vice President and Head Central Engineering, Broadcom 

" We are excited with our expanded collaboration with Synopsys on 7nm and 5nm designs and look forward to continuing the combined efforts to deliver high-volume production designs leveraging Synopsys' Fusion Design Platform. " Read more

Arm

- Ian Smythe
Vice President of Marketing,
Client Line of Business
Arm

" This latest phase of our collaboration will ensure that designers deploying Synopsys' Fusion Compiler can accelerate development of their differentiated products based on Arm's next generation of processors across the entire compute spectrum, from mobile devices to cloud infrastructure. " Read more

Renesas

- Tatsuji Kagatani
Vice President, Shared R&D Division 2, Broad-based Solution Business Unit
Renesas Electronics Corporation

" Synopsys' Fusion Compiler consistently delivered superior power, performance, and full-flow productivity on our production tapeout designs. We are confident that this new Synopsys product will continue to be instrumental to achieving our ambitious goals and help us accelerate innovations for our advanced products. "  Read more

Toshiba

- Seiichi Mori
Senior Vice President
Toshiba Electronics Devices and Storage Corporation

" Compared to conventional technology, we confirmed a 33 percent reduction in timing violations, 10 percent area reduction, and 30 percent less leakage power while cutting the design turnaround time in half. We have completed the integration of Fusion Compiler in Toshiba's design environment. " Read More

Examples of Fusion Compiler Wins

Compute
Mobile
Consumer
AI
Compute + -
Mobile + -
Consumer + -
AI + -

What Our R&D Experts Say

Dr. Tobias Bjerregaard, Director of R&D at Synopsys, discusses how the latest innovations in power-grid integrity, deployed in Fusion Compiler in the form of dynamic-power-shaping (DPS) technology, is efficiently delivering more robust and reliable designs.

Dr. Aiqun Cao, VP of Engineering at Synopsys, discusses how Fusion Compiler’s unified physical synthesis and common optimization framework enables full-flow concurrent clock and data (CCD) optimization, while ensuring physical convergence downstream.

Dr. Henry Sheng, group director of R&D at Synopsys, discusses how Fusion Compiler delivers signoff-accurate PPA on high-performance, low-power designs at advanced nodes, and accelerates design schedules by eliminating late surprises and iterations.

Getting Better Results Faster with the Singular RTL-to-GDSII Product



READ THE ARTICLE

PPA(V): Performance-Per-Watt Optimization with Variable Operating Voltage



Read the White Paper

One Golden-Signoff-Capable Timing Engine to Rule them All



READ THE BLOG

Bold, Different and Smarter: How Synopsys is Innovating to Keep You Ahead of the Curve

Sassine Ghazi, GM of Synopsys’ Design Group, discusses how a revolution in digital design was started by creating a single data model for all design, and he describes how Fusion Compiler, the industry’s only RTL-to-GDSII design product, was formed.

Digital Implementation: The New Way Forward

To provide customers with better PPA and throughput for their design flows, Synopsys has re-invented design implementation with Fusion Compiler™. 

Fusion Compiler is the result of the company’s bold initiative to build a new architecture from the ground up around a single, unified data-model that fuses synthesis, place and route (P&R) and signoff technologies in an unprecedented way to maximize PPA.