The Lynx Design System can be leveraged to create and automate flows for many critical implementation, validation, regression and correlation tasks, enabling engineers to focus on achieving project goals. The comprehensive environment includes:
- Production ready RTL-to-GDSII flow
- Technology process node configuration plug-in
- Optimized processor and interface IP plug-ins
- Library quality assurance (QA) flow
The production ready RTL-to-GDSII flow is tuned to deliver superior quality of results with the Synopsys Design Platform. It allows designers to customize tool capabilities and methodologies based on their specific project needs and integrate third-party tools as needed. For example, designers can configure Synopsys tools such as Design Compiler® Ultra, Design Compiler Graphical, TetraMAX® ATPG, PrimeTime®, IC Compiler, IC Compiler II, IC Validator, StarRC™, VC LP, HSPICE® and NanoTime.This hierarchical, production RTL-to-GDSII implementation ﬂow includes the following features:
- Synopsys Design Platform reference methodologies
- Built-in methodologies for design optimization, including optimizations for low power, area, performance and manufacturability
- Full-chip hierarchical RTL-to-GDSII support
- Validation with multiple standard cell libraries and foundry technology nodes
- Design environment support for job distribution, job submission optimization, revision control and data management
- Project-based deployment model enabling multi-site and multi-user support
- Full technical support and regular updates to the latest tools and methodologies
While the Lynx production flow is tuned to deliver superior quality of results with the Synopsys Design Platform, you can readily incorporate other Synopsys or third-party tools into the design flow by updating standard and well understood TCL scripts.
The technology process node configuration and optimized processor and interface IP plug-ins, along with Library QA flow, are pre-validated scripts and utilities that help accelerate project start and reduce the time it takes to get to optimized design results.
Lynx’s process node configuration plug-in gives designers a template configuration of tool and flow settings to quickly configure the Lynx flow for their choice of standard cell libraries and memories. To further expedite project setup, pre-validated configurations for commonly-used libraries and process nodes are optionally available. They include process technology information and representative flow and tool settings for specific libraries and foundry nodes spanning from 180-nm down to 14-nm.
Processor cores are often the most critical IP block in a SoC, and optimizing the implementation for the best balance of performance, power and area can require a significant amount of effort. To provide design teams with a more productive starting point, Lynx’s optimized processor and interface IP plug-ins include pre-tuned and IP-specific flow scripts, optimized timing and DFT constraints, floorplans and placement guidance, IP-specific tool settings, design and floorplan exploration and comparative analysis flows for leading processor cores and interface IP, including:
- ARM® Cortex™-A7 MPCore
- ARM Cortex-A15 MPCore
- ARM Cortex-A17 MPCore
- ARM Cortex-A53 MPCore
- Imagination Technologies PowerVR™ Series6 GPU Core
- Synopsys ARC® HS34, HS36, and HS38 processors
- Synopsys DesignWare® DDR4, DDR3 and PCI Express® Interface IP
The processor and interface IP specific flows encapsulate the best design practices for optimization and hardening of processor cores and interface IP, shortening design team time to optimized performance, power and area results in chosen process technology.
Mismatched, incorrect, or incomplete technology and library files can negatively impact a design project’s schedule and a designer’s productivity. The risk is especially high at newer process nodes where technology data is constantly changing. The library quality assurance plug-in includes scripts and documentation to configure and pre-test any library and technology files for proper execution in the design flow. These comprehensive data and integration checks help ensure that the incoming library and hard IP are configured correctly in the context of the design.
For questions about the availability of a plug-in for your specific IP and technology process node, please contact firstname.lastname@example.org.