A custom integrated circuit (IC) is sometimes called a full-custom IC. To understand the specific requirements of this type of IC design, we first look at the more typical design process called semi-custom design. Sometimes this process is called application-specific IC, or ASIC design.

Memories, standard cells, and larger macro functions such as processor cores are all examples of these building blocks. Using pre-defined building blocks increases designer efficiency. The design process is one of assembly of the building blocks and verification that the collection of blocks used will satisfy the design requirements. Sophisticated EDA tools are used to create specific versions of the building blocks to address unique requirements. A memory compiler that creates the correct memory size for a given design is an example of this process. Descriptions of digital circuits expressed in high-level languages such as Verilog are automatically “compiled” into the logic elements needed to implement these functions. This is called logic synthesis and is another example of this process. The entire collection of design elements is then placed and routed on the silicon substrate using automated technology.

While this process is very efficient, it creates a circuit that is a “best fit” for the requirements based on the standard building blocks that are available. Sometimes, the “best fit” approach will not meet the goals of the design. For high-precision requirements, where the performance, accuracy, power, or size of the IC is critical, a custom IC design approach is needed.

A custom, or full-custom IC, design process uses unique building blocks that are created specifically for the function required. Many of the same tools are used in a custom IC design process that are used in the previously described semi-custom, or ASIC, design process. The difference is, the building blocks that are assembled are often custom built to deliver specific capabilities. An IC layout editor is an important tool for this kind of design process. The methods used to assemble these devices can also be different to accommodate the unique requirements of the IC or block being developed. 

Importance of Custom ICs

In cases where the performance, accuracy, power, or size of a particular circuit is critical, a custom IC design approach is the only method that will deliver the required capability. Many such demanding requirements exist for analog or power ICs. For example, a high-frequency receiver for a 5G cell phone infrastructure will require custom design due to the specific requirements for signal integrity and accuracy. ICs that switch large amounts of power, such as those found in smart electric meters, also require special design considerations to accommodate the extreme heat and electric fields of these applications.

Custom IC design also finds significant application in the development of the building blocks used in semi-custom, or ASIC, design. The standard cells used in this methodology are typically designed using full custom techniques to ensure maximum density and performance. Since these cells are re-used many times, the extra work to build an optimal design is justified. The low-level storage elements used to build memories (i.e., bit cells) are also built using a custom design process. Another example is the datapath in an embedded processor core. These elements must perform at a high speed to support the operating clock frequency of the processor core. In this case, the elements of the datapath are custom designed so they can be routed by abutment (i.e., all connections line up on the left and right sides of the datapath blocks). This method reduces routing delays to a minimum but requires custom design to facilitate the approach.

How are Custom ICs Designed?

Below are the steps that are required in a custom IC design flow:

  • Architectural Design. Here, the required functionality of the IC or the particular block is specified. What functions must the IC or block deliver? What is the required speed and power consumption? What is the target cost?  The answers to these questions will inform subsequent choices for the specific technology that will be used to implement the device. At this stage, “what” is required is most important.  “How” it will be implemented is still not well defined.
  • Logic / Circuit Design. Here, macro-level building blocks are interconnected to implement the required functionality of the IC or block. The collection of devices is simulated to verify the functionality of the design. Either a digital logic simulator or an analog circuit simulator will be used, depending on the level of simulation detail that is required. During this step, “how” the chip or block will be implemented begins to be defined.
  • Physical Design. During this step, the actual layout of the interconnected shapes that implement all the required circuit elements on the silicon wafer are created. The process begins with a chip “floorplan,”which defines where each of the primary functions of the chip will be located and where the primary input and output ports of the design will be located. If a smaller building block is being designed, this step may be skipped. Next, a custom layout editor is used to implement the physical layout of the actual shapes that will create the circuit on the silicon wafer. Advanced layout editors will provide real-time feedback to the designer on how the layout is impacting power and performance of the design.
  • Physical Verification. This is the final step before the design is sent to manufacturing. All of the physical effects that the manufacturing process adds to the design can now be modeled. Added resistance from wiring, signal crosstalk, and variability in the manufacturing process itself are some of the many items that must be considered here. Will the circuit still work correctly under these stresses? In addition, there are many design rules regarding how the circuit must be physically laid out on the silicon wafer to ensure it will be manufacturable. These design rules are checked at this step as well. Once this process is completed, the design is ready for “signoff,” a step where all of the required checks are verified as correct and the design is submitted to manufacturing or used in subsequent semi-custom or ASIC designs.

Synopsys Custom Design Family

Break free from outdated analog design tools

What Solutions Does Synopsys Offer?

The Synopsys Custom Design Platform is a unified suite of design and verification tools that accelerates the development of robust custom analog designs. Built on the Custom Compiler™ custom design environment, the platform features industry-leading circuit simulation performance, a fast and easy-to-use layout editor, and best-in-class technologies for parasitic extraction, reliability analysis, and physical verification.

Platform tools include:

  • Custom Compiler: providing design entry, simulation management and analysis, and custom layout editing features
  • FineSim:  a multi-core/multi-machine simulator that is well-suited for the simulation of large, complex analog and RF circuits
  • IC Validator: a comprehensive and high-performance signoff physical verification solution that improves productivity for customers at all process nodes
  • HSPICE: the gold standard for accurate on-chip simulation and silicon-to-package-to-board-to-backplane signal integrity simulation and analysis
  • StarRC: the gold standard for parasitic extraction
  • CustomSim: featuring the FastSPICE simulator, which delivers superior verification performance and capacity for all classes of design
  • Custom WaveView: a graphical waveform viewer and simulation post-processing tool for analog and mixed-signal ICs
  • SiliconSmart: a comprehensive array of library characterization and QA capabilities to generate the models required for digital signoff tools such as PrimeTime
  • Reliability Analysis: HSPICE, FineSim, and CustomSim support a comprehensive set of reliability and Monte Carlo analysis features to ensure circuits operate correctly in the face of variability

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