Reliability Analysis

Deliver Robust Designs

With the growth in safety-critical applications and the transition to FinFET process nodes, ensuring design robustness has become challenging. IC designers have to contend with worsening variation and reliability, both at the device and interconnect level. As a result, designers are looking to perform rigorous reliability analysis and even use Monte Carlo analysis, either standalone or in conjunction with MOS aging, to ensure design robustness.

Synopsys Solutions

HSPICE, FineSim, and CustomSim support a comprehensive set of reliability and Monte Carlo analysis features, with the cornerstones being high-performance technology and commonality. The commonality extends across foundry-certified HSPICE models, analysis features, parallel simulation infrastructure, simulation environment, and post-processing utilities, enabling users to easily transition from HSPICE to FineSim and CustomSim to meet varying design verification needs.

Monte Carlo Analysis Highlights

1B+ sample Monte Carlo for leaf cells
Efficient sampling (e.g., SRS, LHS, Sobol)
Sigma amplification to minimize sample size for 3–4.5 sigma analysis
1M+ MOS Monte Carlo for large blocks and mixed-signal subsystems

Reliability Analysis Highlights

Foundry-certified MOS aging with built-in high-performance engines and aging models
Support for third-party foundry and user-defined aging models
Single-step aging-aware Monte Carlo flow for faster TTR
Foundry-certified dynamic electromigration and IR drop analysis, including self-heat-aware flow
Static transistor-level electrical rule checking (ERC)