With the growth in safety-critical applications and the transition to FinFET process nodes, ensuring design robustness has become challenging. IC designers have to contend with worsening variation and reliability, both at the device and interconnect level. As a result, designers are looking to perform rigorous reliability analysis and even use Monte Carlo analysis, either standalone or in conjunction with MOS aging, to ensure design robustness.
HSPICE, FineSim, and CustomSim support a comprehensive set of reliability and Monte Carlo analysis features, with the cornerstones being high-performance technology and commonality. The commonality extends across foundry-certified HSPICE models, analysis features, parallel simulation infrastructure, simulation environment, and post-processing utilities, enabling users to easily transition from HSPICE to FineSim and CustomSim to meet varying design verification needs.
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