Please join us for our 2023 Synopsys Lithography Technical Forum to learn the latest on Synopsys Manufacturing's mask synthesis, mask data prep and lithography simulation solutions.

Monday, February 27, 2023 | 12:30 p.m. – 3:45 p.m. PT.
San Jose Marriott Hotel, Salon IV Ballroom

Why Attend?

Synopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis, Mask Data Preparation, TCAD, and Yield Management tools provide leading edge performance, accuracy, quality, and cost of ownership for all your production and development needs.


Who Should Attend?

The Lithography Technical Forum provides OPC, RET, and MDP engineers and managers practical insight into upcoming industry trends and solutions for delivering the highest quality results from their lithography hardware.

Synopsys Presentations & Posters

Register Today


12: 30 p.m. PST
Registration & Lunch

1:00 p.m. PST​
Welcome & Introduction


1:15 p.m. PST​
Keynote: The Brave New World of Multi-Node Mask Making

We will survey a number of IC trends and developments pushing the mask industry toward a next phase of evolution.   Mask capabilities will be driven not only by traditional roadmap enablement including high NA EUV but also through factors such as global IC supply chain regionalization, a broad expansion of multi-node design activity and emerging applications for chips.  Whether such dynamics really motivate a so-called brave new world for mask making remains to be seen.   What remains clear though is photomasks will continue to play a vital, enabling role in the progress of global IC manufacturing and certain emerging challenges facing the industry will be unprecedented.

Chris Progler, Chief Technology Officer, Photronics Inc.

1:45 p.m. PST​
EUV Lithography Patterning: ​Status and Challenges Towards High NA

Device scaling is continuing by the deployment of the 0.33NA extreme ultraviolet lithography (EUVL) in high volume manufacturing.  To enable technology nodes below 2nm, high NA EUV lithography is under development.​

As the nanoscale is pushed further down, the stochastic nature of the patterning process becomes one of the major patterning roadblocks.  Faster learning cycles on patterning process development are needed to minimize the stochastic patterning defectivity issues.  Etching and thin film processes become essential to a hollistic pattering solutions. This presentation will show the latest development on EUV patterning materials, their challenges and provide insight for overcoming these obstacles as we move towards high NA.

Danilo DeSimone, Principal Member of Technical Staff, IMEC

2:30 p.m. PST​

2:45 p.m. PST​
Curvilinear Mask Solutions for ​EUV Lithography Enablement

The lithographic benefits of improved process window, mask consistency, sidelobe printing control and MRC for curvilinear over Manhattan mask has been demonstrated in DUV and will be extendable to EUV. The prior production limitations of curvilinear masks have been reduced significantly with recent technology advancements in multi-beam mask writers that enabled lower costs and capabilities to meet specifications for advanced patterning nodes including EUV lithography generations. ILT is known for its advantage of creating a patterning-optimized curvilinear mask through field operations.  Proteus ILT, with its decade+ of curvilinear IP technology, has been used to solve the most challenging lithography problems with superior quality.  The next generations of EUV lithography and designs will continue to have challenges in higher pattern density (computational cost), anamorphic imaging and complexity that will need the capabilities of the best computational solution.  In this presentation, various computational solutions and mask synthesis flows for curvilinear mask (ILT, Curve OPC, Hybrid ML ILT + Curve OPC) along with their supporting curvilinear technologies (MRC, data volume control, consistency/symmetry, boundary treatments) will highlight the readiness for these EUV challenges.

Thuc Dam​, Sr. Product Engineering Mgr., Synopsys

3:15 p.m. PST​
Towards the Future of Interconnects: ​From Materials Pathfinding to Bleeding-edge EUV

Nick Lanzillo​, Interconnect Performance Lead, IBM

3:45 p.m. PST​
Closing Remarks

Synopsys Booth

Tuesday, February 28 - Wednesday, March 1, 2023 | San Jose Convention Center

Attendees are invited to visit the Synopsys booth #622 to view the latest innovative technologies and chat with Synopsys experts live! 

Synopsys SPIE activities

Please visit our Sessions & Posters page to learn more about Synopsys