System-on-Chip (SoC) Design Elements Guide

A System-on-Chip (SoC) is an integrated circuit that contains all the required electronic circuits for a fully functional system. We’ve already discussed the basics of SoCs and why they are so critical for the next generation of computing and established many advantages from miniaturization to power efficiency to production methods. However, in this article, we’ll be delving into what exactly goes into creating a System on Chip design. 

SoCs have a variety of blocks that require sending data and instructions and thus require communication subsystems. For a while, traditional data bus architectures were used to connect the different blocks of the SoC.  For example, ARM’s royalty-free Advanced Microcontroller Bus Architecture (AMBA) was a common standard. However, computer buses have limited scalability and support only tens of cores. 

Wire delay is not scalable due to smaller miniaturization; this results in system performance not scaling with the number of cores. For this reason, the SoC’s operating frequency must decrease to remain sustainable. This fact, coupled with more wires consuming more electrical power, has led to adoption of network-on-chip (NoC) technology.

With NoC technology, advantages include application and destination-specific routing, better power efficiency, and reduced bus content. Newer NoC architectures are constantly being developed. For example, distributed computing network topologies such as torus, hypercube, mesh, and tree networks are increasingly popular.  NoC architectures can efficiently meet the power and throughput needs of SoC designs. 

Designing SoCs involves hardware and software to control the processor, peripherals, and interfaces. A strong design workflow develops hardware and software simultaneously in an architectural co-design method.

Concerning hardware, as with integrated circuit design in general, many SoCs are developed using hardware component IP core specifications, known as blocks. Hardware blocks are created using EDA tools and can be classified into the following categories:

• Hard IP cores are hard layouts using physical design libraries but are technology dependent and may lack flexibility.
• Soft IP cores include VHDL/ Verilog code with functional descriptions of IPs, making them more flexible and reconfigurable but requiring synthesis and verification before implementation.
• Firm IP cores strike a balance between the two and are provided as netlists to specific physical libraries after synthesis. 

On the software side, SoCs are designed with high-level programming languages (MATLAB, C++, etc.) and are converted to RTL designs through high-level synthesis tools. These algorithmic synthesis tools allow designers to model and synthesize the system, circuit, software, and verification levels in a single language. 

After architecture is defined, new hardware elements are written and synthesized into register transfer level (RTL), defining the circuit behavior and then connected in HDL, creating the full SoC design.

The SoC must be verified for validation before being manufactured in a foundry, in a process known as functional verification. The verification process accounts for a large portion of the chip design life cycle —up to 70%. Once the chip is fully verified to work as intended, it is sent to the foundry for mass production.

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