With the growth in complexity of FPGA designs and higher integration of complex IP, it is becoming increasingly more difficult to verify these designs. Current analysis is limited by timing verification, functional simulation and a cumbersome manual review process. Additionally, due to the integration of complex IP (SERDES, PCIe and USB), the number of asynchronous clocks in FPGA designs has also increased significantly.
Clock Domain Crossing issues have become a leading cause of FPGA design errors, which adds significant time and expense to the design-and-debug cycle. These errors are intermittent and very difficult to debug during the development process.