- All Products
- Software Integrity
- Semiconductor IP
- Verification
- Design
- Silicon Engineering
- Application Security Services
- Dynamic Analysis (DAST)
- Mobile Application Security
- Penetration Testing
- Managed Static Analysis
- All Services
- Software Security
- Silicon Design
- Community
- About Us
< All Products
< All Products
< All Products
< All Products
< All Products
< All Products
< overview
All Products
+
Software Integrity
+
Semiconductor IP
+
Verification
+
Design
+
Silicon Engineering
+
Optical Solutions
< Software Integrity
< Software Integrity
Application Security Services
Dynamic Analysis (DAST)
Mobile Application Security
Penetration Testing
Managed Static Analysis
< Software Integrity
< Software Integrity
< Software Integrity
Blog
< Software Integrity
Support
< overview
Software Integrity
+
Application Security Products
+
Application Security Services
+
Resources
+
Training & Education
Blog
Support
< Semiconductor IP
< Semiconductor IP
Memories & Libraries
Logic Libraries
Memory Compliers
Duet Packages
HPC Design Kit
Embedded Test & Repair
Non-Volatile Memory
< Semiconductor IP
< Semiconductor IP
Processor Solutions
ARC Processors
Embedded Vision Processors
Development Tools
Operating Systems
Ecosystems
ASIP Tools
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< Semiconductor IP
< overview
< Verification
< Verification
< Verification
< Design
< Design
< Design
< overview
< Silicon Engineering
< overview
< main menu
< Solutions
< Solutions
Industry Solutions
Automotive
Cloud Computing
Financial Services
Industrial Controls Systems
Healthcare
< Solutions
< overview
< All Services
< All Services
< All Services
< overview
< Software Security
< Software Security
Managed Services
< Software Security
Program Development & Design
Maturity Model (BSIMM)
Maturity Action Plan (MAP)
Policies & Standards
Security Metrics
Software Security-in-a-Box
< Software Security
< Software Security
Support
< overview
Software Security
+
Software Security Services
Managed Services
+
Program Development & Design
+
Training
Support
< Silicon Design
< Silicon Design
< Silicon Design
< Silicon Design
< main menu
< Community
< Community
< Community
< Community
Interoperability
ARC Access
HAPS Connect
HSPICE Integrator
In-Sync
System-Level Catalyst
TAP-in
VC Apps Access
< Community
< Community
< Community
< overview
Community
+
Community
+
SNUG
+
Partners
+
Interoperability
+
Academic Programs
+
Company Blogs
+
BSIMM
< About Us
< About Us
< About Us
< About Us
< About Us
SpyGlass for FPGA Designs
Asynchronous Clock Domain Crossing Analysis
Among the many verification challenges confronting FPGA designers, clock domain crossings (CDC) ranks near the top in difficulty. Today’s designs have dozens of asynchronous clock domains, making it difficult to verify using conventional simulation or static timing analysis (STA). The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.
Introduction
With the growth in complexity of FPGA designs and higher integration of complex IP, it is becoming increasingly more difficult to verify these designs. Current analysis is limited by timing verification, functional simulation and a cumbersome manual review process. Additionally, due to the integration of complex IP (SERDES, PCIe and USB), the number of asynchronous clocks in FPGA designs has also increased significantly.
Clock Domain Crossing issues have become a leading cause of FPGA design errors, which adds significant time and expense to the design-and-debug cycle. These errors are intermittent and very difficult to debug during the development process.
Metastability Issues Due to Asynchronous Clock Domain Crossing
Event