SpyGlass for FPGA Designs

Asynchronous Clock Domain Crossing Analysis

Among the many verification challenges confronting FPGA designers, clock domain crossings (CDC) ranks near the top in difficulty. Today’s designs have dozens of asynchronous clock domains, making it difficult to verify using conventional simulation or static timing analysis (STA). The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.


With the growth in complexity of FPGA designs and higher integration of complex IP, it is becoming increasingly more difficult to verify these designs. Current analysis is limited by timing verification, functional simulation and a cumbersome manual review process. Additionally, due to the integration of complex IP (SERDES, PCIe and USB), the number of asynchronous clocks in FPGA designs has also increased significantly.

Clock Domain Crossing issues have become a leading cause of FPGA design errors, which adds significant time and expense to the design-and-debug cycle. These errors are intermittent and very difficult to debug during the development process.

How SpyGlass for FPGA Designs can fix metastability issues due to asynchronous clock domain crossing

Metastability Issues Due to Asynchronous Clock Domain Crossing