SpyGlass Constraints

Specify Early, Validate Continuously and Automate Handoff

Quality of constraints dictates the quality and speed of implementation. Constraints impact is multidimensional spanning synthesis, timing analysis, and physical design. More than 25 percent of design projects go through more than ten iterations due to constraints issues. The burden of overall constraints effectiveness is on the design engineers across the development process. The SpyGlass® Constraints solution addresses these challenges with a broad-based solution starting early in design process and providing an environment to validate continuously.

Download Datasheet

Introduction

Creating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints, managing thousands of lines of legacy constraints, managing thousands of timing exceptions, experiencing unwanted iterations due to changing constraints and implementing erroneous constraints resulting in redesigns or even respins.

The SpyGlass Constraints solution provides a productivity boost to IC design efforts by automating the validation of constraints. SpyGlass Constraints verifies that existing constraints are correct and consistent early in the design flow.

The SpyGlass solution can trim weeks or more from design schedules by pinpointing the root cause of constraint problems. By ensuring valid constraints, SpyGlass Constraints can eliminate design flaws and costly respins.

Features and Benefits

• Ensures that constraints are correct and consistent throughout the design flow, early at RTL
• Can save weeks or months of manual creation and verification effort
• Supports full Tcl-based SDC, compliant with Design Compiler® and PrimeTime®
• Flags redundant and over-specified constraints

News

Synopsys Announces Next-Generation VC SpyGlass RTL Static Signoff Platform

Synopsys VC LP for Low Power Signoff Verification Delivers Up To 5X Runtime Gain at Samsung

Event

VC Formal SIG Asia-Pacific
July 21, 2020

Webinars

Avoid Silicon Respins Using RDC Techniques (Taiwan)

Introduction to Formal Verification (Chinese)

Faster Formal Verification Closure for Datapath in AI & Processor Designs

White Papers

Shift Left Verification with Comprehensive Lint Signoff

Achieving CDC Signoff on Multi Billion Gate Designs with Hierarchical CDC Flow