SpyGlass Constraints

Specify Early, Validate Continuously and Automate Handoff

Quality of constraints dictates the quality and speed of implementation. Constraints impact is multidimensional spanning synthesis, timing analysis, and physical design. More than 25 percent of design projects go through more than ten iterations due to constraints issues. The burden of overall constraints effectiveness is on the design engineers across the development process. The SpyGlass® Constraints solution addresses these challenges with a broad-based solution starting early in design process and providing an environment to validate continuously.


Creating and ensuring correct and consistent constraints, at all levels of the design hierarchy and throughout the design cycle, is a vital and increasingly challenging task. The difficulties can include: writing new constraints, managing thousands of lines of legacy constraints, managing thousands of timing exceptions, experiencing unwanted iterations due to changing constraints and implementing erroneous constraints resulting in redesigns or even respins.

The SpyGlass Constraints solution provides a productivity boost to IC design efforts by automating the creation and validation of constraints. SpyGlass Constraints generates new constraints where needed and verifies that existing constraints are correct and consistent early in the design flow.

The SpyGlass solution can trim weeks or more from design schedules by pinpointing the root cause of constraint problems. By ensuring valid constraints, SpyGlass Constraints can eliminate design flaws and costly respins. The solution also creates a smooth handoff between tools in multi-vendor flows. Advanced options streamline constraints management tasks by automating timing exception generation and verification.

SpyGlass RTL Signoff

Features and Benefits

  • Automatically creates and verifies constraints
  • Ensures that constraints are correct and consistent throughout the design flow, from RTL through floor planning
  • Validates consistency and correctness at all levels: chip-to-block and block-to-block
  • Can save weeks or months of manual creation and verification effort
  • Supports RTL and netlist input
  • Supports full Tcl-based SDC, compliant with Design Compiler® and PrimeTime®
  • Flags redundant and over-specified constraints
  • Advanced options automate timing exception generation and verification