SpyGlass RDC

Comprehensive, Low-Noise Reset Analysis

Clock domain crossings (CDCs) are a well-known source of metastability. However, they are not the only source. Asynchronous reset crossings within a same clock domain can also cause metastability. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up boot sequences. As a consequence, Reset Domain Crossing (RDC) issues are causing more and more design errors. Such errors can add significant time and expense to the design and debug cycles, and may even find their way into the silicon, necessitating costly respins. Like CDC verification, RDC verification is equally important to ensure that the designs work as expected. For both of these, you need a high-powered, comprehensive solution.

Comprehensive RDC Analysis

SpyGlass® RDC provides the comprehensive solution to address reset crossing domain issues early at RTL. This solution avoids costly respins and:

  • Leverages industry standard SpyGlass CDC architecture
  • Offers simple setup to automatically extract the clock, reset and clock domain information
  • Recognizes standard design techniques resulting in the lowest number of false violations
  • Provides high-performance runtime and RDC-centric debug capabilities
  • Offers short learning curve and easy adoption into existing workflows
  • Integrates within the SpyGlass RTL signoff solution which targets other analysis, for lint constraints, DFT and power
  • Offers hierarchical SoC flow to support IP-based design methodologies to deliver fastest turnaround time for very large SoCs
SpyGlass RTL Signoff