Clock domain crossings (CDCs) are a well-known source of metastability. However, they are not the only source. Asynchronous reset crossings within a same clock domain can also cause metastability. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up boot sequences. As a consequence, Reset Domain Crossing (RDC) issues are causing more and more design errors. Such errors can add significant time and expense to the design and debug cycles, and may even find their way into the silicon, necessitating costly respins. Like CDC verification, RDC verification is equally important to ensure that the designs work as expected. For both of these, you need a high-powered, comprehensive solution.