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Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.
CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly respins. Besides the traditional CDC issues, Reset Domain Crossing (RDC) issues can also cause metastability in signals. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more information about these reset domain crossing capabilities.) For both of these types of issues, SpyGlass® provides a high-powered, comprehensive solution.