This course will show you how to use PrimePower to effectively analyze average and peak power for UPF and normal designs with guidelines for different activity annotations.
This course covers a recommended Static Timing Analysis (STA) methodology using PrimeTime to generate STA reports that are based on validated timing constraints.
This is an introductory course to signoff extraction using StarRC. You will learn how to use StarRC for extracting gate level and transistor level design flows.
In this course you will learn how to use TetraMAX® to perform ATPG on a post-layout chip netlist scan design.
NEW FreeView IC Compiler II: Block-level Implementation eLearning
NEW SystemVerilog for RTL Design eLearning
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