A common data model allows early- and late-stage tools in an EDA flow to share information. This facilitates a shift-left approach to design, which results in a more convergent, predictable design process since early-stage results can now take late-stage effects into account. The concept of physical synthesis, where placement information and routing delays are more accurately modeled during logic synthesis, is an example of this approach. Propagating RTL design intent throughout the flow has significant benefits as well. For example, RTL design intent can make late place-and-route stage, multi-bit re-banking much easier. Without this intent, the tool is looking at a random sea of logic to bank. A common data model also implements a “design memory” effect, where approaches that didn’t work well can be propagated so they are avoided for similar future cases.
Convergent design flows result in a more efficient design process with less re-work and a shorter time-to-market. This has a significant positive impact on the lifetime profitability of the system using the chip being designed. Pervasive use of a well-developed common data model opens another significant benefit. Every chip design project is different, and every design group has a specific way of addressing these unique challenges. If the team uses tools that are based on a well-developed common data model, it now becomes possible for the design group to develop its own flow and its own strategy for sharing early- and late-stage data.
The result is a fully targeted and customized design flow. We call this a customer-defined, hyper-convergent design flow. It represents one of the most potent tools available to target the precise needs of a complex chip design project.