Must Attend Event

Join us for the Signoff Special Interest Group (formerly PrimeTime SIG) in-person event on November 2, 2023 in Sunnyvale, CA.  This technical event will supercharge your design closure process and empower you to tackle the most intricate design challenges. This year’s event will have two dedicated tracks.  Track one - Signoff, will explore the latest technology advancements in timing, power, extraction, and ECO.  Track two - Physical Signoff & ESD, focus's on the latest innovations in DRC, LVS, RC extraction, power devices, and ESD areas. You will hear from industry experts on breakthrough techniques and methodologies that accelerate design closure for advanced node digital and analog designs. Don’t miss this opportunity to engage in technical discussions, share insights, and collaborate with like-minded professionals. Register to attend today. 

 

Thu. November 02, 2023
11:30 - 12:15 AM PDT
Registration Check in & Lunch
Thu. November 02, 2023
12:15 - 12:50 PM PDT
Synopsys Signoff Vision
  • Jacob Avidan, Senior Vice President, Engineering, Synopsys
Signoff Track
Thu. November 02, 2023
12:55 - 01:20 PM PDT
Distributed STA and ECO for Next Generation Hyperscaler Designs
  • Sarvesh Ganesan - Microsoft
Signoff Track
Thu. November 02, 2023
01:20 - 01:45 PM PDT
PrimePower+ Power Replay Flow
  • Vishnu Pothireddy  - Cisco Systems
Signoff Track
Thu. November 02, 2023
01:45 - 02:10 PM PDT
Leveraging PrimeShield Voltage Slack Analysis To Build Vmin Robust Designs and Explore the Lowest Possible Vmin Reduction
  • Muniswara (Munish) Raja - Intel
Physical Signoff & ESD Track
Thu. November 02, 2023
12:55 - 01:15 PM PDT
Performance Improvements at Full Chip Level using IC Validator Elastic on Intel XEON Design
  • Matt Nichelson - Intel
Physical Signoff & ESD Track
Thu. November 02, 2023
01:15 - 01:45 PM PDT
Unlocking the Potential: Advanced StarRC Extraction Methodologies for Accurate Custom/RF Design Closure
  • Krishnakumar Sundaresan - Synopsys
Physical Signoff & ESD Track
Thu. November 02, 2023
01:45 - 02:10 PM PDT
Improving Design ESD Robustness with Full Chip CDM Simulation
  • Srinivas Velivala - Synopsys
Thu. November 02, 2023
02:10 - 02:25 PM PDT
Signoff Track
Thu. November 02, 2023
02:25 - 02:50 PM PDT
Hyperscale Based Large Subsystem Timing Closure using Synopsys Tweaker ECO
  • Ramesh Murugesan - NVIDIA
Signoff Track
Thu. November 02, 2023
02:50 - 03:15 PM PDT
IR Aware STA for Advanced Process Nodes
  • Srinivas Chilukuri - Qualcomm
Signoff Track
Thu. November 02, 2023
03:15 - 03:30 PM PDT
Migrating to Synopsys PrimeClosure
Physical Signoff & ESD Track
Thu. November 02, 2023
02:25 - 02:50 PM PDT
Improving PMIC & Power Transistor Design Efficiency & Reliability in Advanced Technologies
  • Philipp Lindorfer - Synopsys
Physical Signoff & ESD Track
Thu. November 02, 2023
02:50 - 03:10 PM PDT
Synopsys IC Validator Productivity Features for Faster Signoff
  • Ramulu Undevalli - NVIDIA
Physical Signoff & ESD Track
Thu. November 02, 2023
03:10 - 03:30 PM PDT
Synopsys IC Validator Demo
Thu. November 02, 2023
03:30 - 04:30 PM PDT
Networking Reception

Location Details

Please park in the Synopsys Parking Garage: 645 Palomar Ave, Sunnyvale CA, 94085

After parking in the garage cross Palomar Ave to  Synopsys HQ, Building 1: 800 N Mary Ave , Sunnyvale, CA 94085

Follow signs to the check-in and badge pick up.  Please bring a photo ID for check-in. 

Synopsys HQ Map