Any Tool. Any Scale. Any Time.
PrimeTime/RedHawk-SC IR-Drop Aware Voltage-Timing Solution
Ayhan Mutlu - Ayhan Mutlu, Principal Engineer, Synopsys
Jongyoon Jung, Principal Engineer, Samsung Foundry
Continuous reduction of the supply voltage coupled with the increase in metal layer resistivity make design timing more sensitive to the IR drop across the power grid. Conventional single voltage timing sign off techniques either fail to capture these IR drop effects or accounts them through pessimistic timing derates. In this presentation, we will cover PrimeTime® solution's path level timing analysis incorporating Ansys RedHawk®-SC IR drop analysis results to analyze IR drop impact on timing. The solution uniquely identifies voltage sensitive paths and enables highly accuracy analysis of voltage drops and ground bounces along the timing paths.
Efficient and High-Performance Physical Verification on Cloud
Manoz Palaparthi, Sr. Staff Product Marketing Manager, Synopsys
For today’s advanced node designs, physical verification sign off is complex and time consuming. Scaling to many CPU cores using cloud resources can significantly speedup the full chip signoff job. Running a physical verification job in the cloud presents a unique set of challenges. In this presentation, we will explore solutions to those challenges by demonstrating how to setup IC Validator physical verification on Samsung SAFE Cloud Design Platform and scale to hundreds of CPU cores to achieve fastest performance. We will also highlight how to optimize compute resource usage when scaling DRC job in the cloud using IC Validator’s elastic CPU technology.
PrimeSim GPU Technology That Changed the Landscape of Simulation Performance
Tom Hsieh, Sr. Manager Application Engineering, Synopsys
Leverage latest advancement in GPU based technology in transistor level simulator to significantly speed-up design verification. The PrimeSim™ Circuit Simulator performance evaluation was conducted in comparison to the existing sign off circuit simulator through the simulation engine improved by PrimeSim in Samsung Foundry AMS Design IP by using GPU Simulation. Synopsys's GPU-based next-generation Circuit Simulator PrimeSim is expected to enhance Samsung Foundry AMS design infrastructure.
Best Practices To Accelerate Tapeouts of Advanced Arm-Based SoCs Targeting the Latest Samsung Foundry Technology Nodes
Paul Gittinger, Sr. Staff Applications Engineer, Synopsys
In this session you will learn about the latest technologies in Synopsys Fusion Compiler™ being developed and deployed in close collaboration with Samsung Foundry and Arm. It enables optimized implementation of advanced Arm®v9 architecture based processor with Arm POP™ IP for Samsung 4LPP Technology.
Enabling Access for ATE and In-Field Use Cases Via High Speed Functional Interfaces Such as PCIe and USB
Randy Fish, Director of SLM Marketing, Synopsys
The complexity of SoCs today combined with the demands on test metrics continue to drive the volume of data required to test a component. The majority of designs today have access to PCIe® or USB interfaces that are used as part of the device’s mission mode of operation. Leveraging these high speed functional interfaces provides value during the In-Test and In-Field phases of IC’s lifecycle. Through the use of existing high speed functional interfaces, SoCs no longer require the large number of dedicated GPIOs to perform test and have a clear path to scaling test data throughput. Utilizing the same IOs, tests can be reapplied and modified during the device’s In-Field operation for incremental testing, retesting, debug, and system optimization. Synopsys has collaborated with Samsung Foundry to deliver the IP (DesignWare® High Speed Access and Test) and software (TestMAX ALE) necessary to enable Samsung Foundry customers to test via PCIe and USB. We will explain the methodologies, technologies, and use cases associated with these products.
3D Silicon stacking for high performance computing using 3DIC Compiler Design Platform
Sutirtha Kabir, Director of Product Engineering, Synopsys
The growth in high-performance computing is driving the adoption of advanced 2.5D packaging and 3D stacking technologies to meet increased system-level design challenges including more functionality, higher performance, lower power, smaller form-factor, and reduced cost. Architectures with memory connecting directly to a compute complex through hybrid bonds and Through Silicon Via’s deliver the required boost in performance and power efficiency while meeting the transistor density and cost constraints. In this session, Synopsys will share the highlights of its collaboration with Samsung on advanced multi-die design and present system-level co-design and analysis methodology for early evaluation, planning and implementation of 3D IC designs, using 3DIC Compiler and Ansys’ RedHawk EMIR and thermal solutions.
Significant ECO Iteration and Turnaround Time Reduction for Fast PPA Closure
Mihir Kumar, Director Application Engineering, Synopsys
The power, performance, area, (PPA) requirements at advanced node designs have stringent thresholds which leaves very little tolerance for timing errors and poor ECO quality of results. In addition, advanced process nodes have much more complicated physical rules to meet, which leads to a higher number of scenarios that need to be accounted for to ensure a successful design closure. Every ECO change can potentially become a bottleneck and influence the tape out schedule. The ECO solution needs to effectively identify, analyze, fix, and recover all of the potential issues in chip performance, power, area and reliability. Synopsys introduced multiple innovations in the ECO Closure area which reduce the turnaround time without causing any accuracy loss. This paper will cover the of Tweaker ECO and PrimeECO on advanced node designs, where more than 2X turnaround time was achieved without any sacrifice in QoR.
High-Performance Mobile SoCs Using USB-C 3.2 & eUSB2 IP for Samsung Foundry 4nm Process
Gervais Fong, Director, DesignWare IP Product Marketing, Synopsys
The next generation of smart phones will be expected to deliver an “office in your pocket” for consumers. Using the phone or phablet’s USB Type-C connector, they will be able to forgo a laptop and connect directly to a hub for monitors, mouse, keyboard, and other peripherals. To bring this to market, Samsung and Synopsys have collaborated to provide mobile SoC designers high-quality DesignWare USB IP optimized for Samsung’s process technologies. In this presentation, we will describe the architecture of a mobile SoC that integrates both 20Gbps connectivity and low-power USB 2.0 using USB-C 3.2/DisplayPort and eUSB2 IP. We will also share silicon results of the DesignWare USB-C 3.2/DisplayPort and eUSB2 IP on the Samsung 4nm process.
Optimizing High Performance Computing SoC Designs Using Multi-Rate PHY IP on Samsung Processes
Manmeet Walia, Director of Marketing, Synopsys
Hyperscale data centers are processing and storing growing amounts of data to execute complex workloads, requiring high-performance NRZ PHY IP technologies operating at 32Gbps. Synopsys and Samsung are collaborating to develop high-quality IP that supports multi-rate transceivers for complex, data intensive SoC designs on Samsung’s advanced process technologies. This session features Synopsys’ Multi-Protocol 32G PHY IP on Samsung’s 10-nm, 7-nm, 5-nm, and 4-nm processes that designers can integrate in their SoCs to ensure lowest latency, maximum power efficiency, high bandwidth, and reliable channel performance. The Synopsys PHY IP supports multiple electrical standards, including PCI Express (PCIe) 5.0, 1G to 400G Ethernet, CCIX and CXL, offering the utmost in design flexibility.
Case Study: Enabling HPC Data Center SoCs with DesignWare Foundation IP and Fusion Compiler on Samsung Foundry 8LPP
Josefina Hobbs, Sr. Product Marketing Manager, Synopsys
High-performance computing SoCs host hundreds of large CPUs operating at different frequencies in multiple voltage domains and speeds. To support multi-voltage, multi-domain requirements and control leakage and power, designers can take advantage of specially tuned logic libraries and ultra-fast memory cache instances to achieve their specific PPA goals. In this presentation, we will describe a case study of a complex SoC design that integrated 2.2M instances for a high-performance core. The combination of high-performance memory cache instances, high performance compute logic libraries with large MUXes, hand-tuned complex combinational cells, optimized flops, and 72X and 168X high drive buffer cells for clock spine implementation resulted in excellent 1.62GHz FMAX with a balanced VT-profile. To reduce latency, data center SoCs require very fast searches and Synopsys high-performance and low-power TCAMs can fulfill this need. In addition, Synopsys Fusion Compiler™ provided a unified RTL-to-GDSII environment, resulting in 1.5X faster implementation with a hyper-convergent design flow and 16-core scalability.