Samsung Foundry Forum & SAFE Forum

Why Attend?

Samsung Foundry Forum and SAFE Forum offer designers access to keynotes and technical sessions covering EDA, IP, Design Solution Partners, Cloud and Packaging. The events offer the opportunity to expand their knowledge and inspire ideas for future designs using Samsung Foundry Technology .

  • October 3, 2022: San Jose, USA (Foundry Forum)
  • October 4, 2022: San Jose, USA (SAFE Forum) 
  • October 7, 2022: Munich, Germany (Foundry Forum)
  • October 18, 2022: Tokyo, Japan (Foundry Forum)
  • October 20, 2022: Seoul, Korea (Foundry Forum)
  • October 21- Dec 31: Online platform available

Who Should Attend?

This event provides an opportunity for SOC Designers & System Architects, Business Decision Makers, Executives, Analysts; EDA, IP, Cloud, DSP and Packaging experts to learn and network.

Keynote Spotlight

Sassine Ghazi, President & COO, Synopsys

                                                                                                                           

 

Collaboration Opportunities to Achieve 1,000X – Unlocking Innovation Potential

October 4, 2022 | 10:15 a.m.

Semiconductor chips and software have been the most uplifting phenomena in the history of humankind. While software has defined new products, markets and user experiences, hardware has been at the heart of this innovation. Semiconductor chips deliver the promise of new software innovation and bring it to life. Getting to the next level of world-changing products will require achieving 1,000X for this process. Sassine Ghazi explores the design transformations that must be conquered to achieve this goal. It turns out collaboration is a critical ingredient to success.

 

Synopsys Presentations

Collaborations of DTCO (Design-Technology Co-Optimization) in Samsung Foundry 3nm Technology
James Ban, Director of R&D, Synopsys

Samsung Foundry (SF)'s 3nm technology helps to overcome the performance limitation of FinFET, to improving the power efficiency by allowing the supplying voltage lower, and to minimize the chip-size by using the less instances with the better drivability in transistor. The beauty of SF 3nm is to modulate the gate width of the nanosheet, which is called with Multi-Bridge-Channel FET (MBCFET™), in order to give another optimization variable to tune the performance and power. To boost PPA (Performance, Power and Area) gain in 3nm, SF and Synopsys has been engaging DTCO (Design Technology Co-Optimization) collaboration and co-developed key enablement features and methodologies. This presentation highlights SF and Synopsys collaboration in 3nm GAA technology including key enablement features, PPA efforts in both HP (high performance) and HD (high density) libraries, test vehicle, reference flow and more.


Vertical 3D System Integration, The Next Big Step in IC Evolution
Kenneth Larson, Director of Product Marketing, Synopsys

Vertical 3D system integration has become a hot topic for leading semiconductor companies. The growing use of High Bandwidth Memory (HBM3), and disaggregation of very large dies into chiplets has enabled a substantial reduction in multi-die system design cost.  But the real payoff with 3D system integration is the higher performance with increased density and energy efficiency, in a smaller physical form factor.  Synopsys has enabled the industry to evolve from 2D to 3D designs. In this session, we explore the challenges of 3D design, power, integration, testing, verification, and implementation and how Synopsys and Samsung work together to enable chipmakers in mobile, HPC and AI to reap the benefit of vertical multi-level integration and 3DIC.


Accelerating Advanced Node Analog and RF Design for 5G/6G, Automotive and High-Performance Computing
Denis Goinard, Director of Applications Engineering, Synopsys

Analog and RF circuits are integral to advanced node applications such as 5G/6G, automotive and high-performance computing. Samsung and Synopsys have developed a design reference flow that streamlines RF and analog design. We will present a proven methodology for analog and RF design that spans schematic design, simulation, layout, extraction, electromagnetic (EM) simulation and physical verification using tools from Synopsys and other EDA vendors. We will also share details about the associated Design Solutions Kit (DSK), which includes a set of application notes, tutorials and design examples that cover advanced design methodology topics for RF/Analog design.


Study on Samsung Foundry 3nm Technology and Design via ML-based DSO.ai
James Ban, Director of R&D, Synopsys

As the technology node scales down below nanometer, the design rules significantly increase, which in turn results in the huge search problems in early technology and design. ML (machine learning) is a powerful technique when tuning and optimizing such complicated parameters in technology and design. Synopsys DSO.ai (Design Space Optimization AI) is an early innovator of ML in EDA (Electronic Design Automation) area, where the tool uses advancements of RL (Reinforcement Learning) to effectively search the massive design space for global near-optimal targets. In this presentation, we reports DSO.ai applications on Samsung 3nm technology and designs, such as PPA improvements in both HP (high performance) and HD (high density) libraries, NDR (non-default rule) routing on both clock and signal nets, LP (layer promotion), density control, routing wire and via cost tuning, and more. 


Accelerated Design-to-Signoff with ML/AI Technologies in the Fusion Design Platform
Arvind Narayanan,  Senior Director of Product Marketing, Synopsys

Advanced node complexity, aggressive time-to-market targets, and global engineering resource crunch stresses the design-to-silicon implementation and signoff flows. In this session, we will highlight the AI / ML advancements in the Fusion Design Platform that accelerates the design development and silicon closure of next-gen SoC’s with optimal power, performance and area (PPA). Topics include ML technologies within Fusion Compiler & IC Compiler II such as ML driven delay prediction, macro placement and congestion prediction, the unique DSO.ai solution that simplifies design optimization search space exploration and the newly launched Synopsys DesignDash system for big data analytics using machine learning.


Accelerating High-Performance Compute SoC Designs using PCI Express 6.0 IP on Samsung 4nm Process
Manmeet Walia,  Director of Product Marketing, Synopsys

High-performance compute (HPC) systems deliver parallel processing capabilities to generate detailed and valuable insights for applications as diverse as genome sequencing and engineering modeling. These bandwidth-hungry applications with complex data workloads require HPC SoCs that offer fast data transfer and low latency with high-speed interfaces like PCI Express® 6.0. This session highlights Synopsys’ high-quality PCIe 6.0 IP solution for Samsung’s 4LPP process. The PHY, Controller, and Integrity and Data Encryption (IDE) IP is optimized to support the latest PCIe 6.0 specification including PAM-4 signaling, FLIT mode, L0p power state, security features, and more.


Power-Efficient USB, DisplayPort & eUSB2 for Mobile SoCs on Samsung 3nm Process
Gervais Fong, Director of Product Marketing, Synopsys

As the market for higher-performance and lower-power consumer devices grows, chip designers are looking for an edge that can help them leapfrog the competition. Samsung and Synopsys have collaborated to provide mobile SoC designers with high-quality DesignWare USB and DisplayPort IP optimized for Samsung’s process technologies, including 4LPE and 3GAP. In this presentation, we will describe the architecture of a mobile SoC that integrates both 20Gbps connectivity and low-power USB 2.0 using USB-C 3.2/DisplayPort and eUSB2 IP. We will also share silicon results of the IP on the Samsung 3GAP process.


4LPP TCAMs: Necessary for High-Performance Computing SoCs
Rahul Thukral, Product Marketing Manager, Senior Staff, Synopsys

Rising demand for cutting edge mobile, IoT and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when the device is not active (leakage power). And of course, this power efficiency must be achieved without impacting performance or area. This session will share how Synopsys Foundation IP memory compilers and logic libraries for Samsung's 4LPP process enable SoC designers to achieve the best possible PPA, getting the maximum possible performance out of their designs while taking them to the lowest possible operating voltages, thus significantly reducing overall power consumption.


Booth

You will have the opportunity to visit our in-person booth for additional insight and to connect with us directly.