Sponsored Tutorial - The Next Frontiers of Formal Verification

Presenters: Synopsys, Google, NXP, NVIDIA, Qualcomm

Date & Time: Monday, February 27 – 1:30-5:00pm

Abstract: It’s taken a few decades for formal verification to expand beyond a tool reserved for the select few with a Ph.D. to become a mainstream verification solution. In recent years, formal adoption has compounded due to the following trends:​

• Ever-increasing design complexity affecting coverage closure, making formal verification a must-have strategy in the overall verification flow;​

• Formal applications targeting well-defined domains do not require formal expertise, such as reachability analysis, connectivity checking, control register verification, and X-propagation;​

• Advanced formal applications, such as functional safety, security, low power, are expanding usage to critical design and verification problems;​

• The role of machine learning to increase performance and capacity of the formal engines enabling its use for larger and highly complex designs;​

• Leveraging the cloud to scale the use of formal methods across thousands of CPU cores.​

• Formal verification is like a diamond in the rough with exceptional potential to become as widely used as functional simulation. In this tutorial, attendees will learn about the advanced formal applications and hear first-hand what lies ahead, such as:​

• Solving complexity challenges using advanced formal techniques​

• Using formal methods to detect security leak at the SoC level​

• The advantage to using formal for architectural verification​

• Verifying the most complex datapath blocks, such as wide floating point math functions ​

• The need for model checking C/C++ models​

• And more …​

Attendees will hear from experts in formal verification at industry-leading companies and walk away with a comprehensive understanding of advanced formal technologies and how to apply them across IP/block, subsystem, and SoCs. ​

Sponsored Workshop - Accelerate Coverage Closure from Day-1 with AI-driven Verification

Presenters: Synopsys, Qualcomm

Date & Time: Thursday, March 2 – 9:00-10:30​ am

Abstract: Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Verification engineers use various criteria such as bug rates and coverage metrics or at least asymptotically converge toward target goals to determine when to signoff. In this ‘lecture style’ workshop, we present AI-driven verification, known as Intelligent Coverage Optimization (ICO). The workshop will demonstrate how verification engineers can benefit from early adoption of ICO’s simple use model, part of Synopsys VCS simulator, to accelerate coverage convergence, expose bugs early in the design cycle, reduce debug effort and improve verification turnaround time, thereby maximizing project resource utilization while reducing the verification schedule. ICO leverages modern artificial intelligence (AI) and machine learning (ML) technologies to help optimize coverage and stabilize the testbench. Through continuous feedback, the testbench is stabilized faster with each verification cycle and as more project experience is accumulated. In this workshop, we will present a real case study showing how the entire verification process shifted left using ICO early in the cycle. Employing AI-driven verification techniques reduced the manual effort to write directed tests, helping find bugs faster, and required fewer regression iterations to reach the target metrics, saving ~2 weeks of efforts and up to 15% reduced peak demand of grid resources.​

Sponsored Workshop - The Growing Need for Protocol Solutions to Conquer Verification from IP to Multi-die Systems​

Presenters: Varun Agrawal, Synopsys; Shakir Ali​, Synopsys

Date & Time: Thursday, March 2 – 11:00am-12:30pm

Abstract: With ever increasing chip design complexity, including chips for domain-specific applications, the role of on-chip and off-chip protocols have increased drastically. Protocol versions are evolving very rapidly to meet application needs for bandwidth, latency, and coverage. Verifying these protocols for behavior, performance, and power in the context of real application payloads and usage scenarios is an absolute necessity.​

In this workshop, we will discuss how protocol verification is becoming more and more challenging as designs evolve from IP blocks to multi-die system setups and why IP verification is no longer enough. An end-to-end protocol is essential to validate protocol behavior and fulfill verification requirements for IP through system designs. We will walk through uses cases for when to apply virtual models, speed adapters, virtual transactors, and protocol interface cards to exercise interfaces from IP to systems. We will also discuss various power, performance and pre-to-post silicon continuity use cases that are enabled with an end-to-end protocol verification solution. ​

Accelerating Functional Verification through Stabilization of Testbench Using AI/ML           ​
Srikanth Vadanaparthi, Qualcomm; Pooja Ganesh, Qualcomm; Dharmesh Mahay, Synopsys; Malay Ganai, Synopsys​

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Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus (PSS) for IP Validation     ​
Robert Martin, Intel Corporation; Alan Curtis, Intel Corporation; Gopinath Narasimhan, Synopsys; Qingwei Zhou, Intel​

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Verification Macros: Maintain the integrity of verifiable IP UPF through integration​
Amit Srivastava, Synopsys Inc; Shreedhar Ramachandra, Synopsys Inc