EDA
System
IP
SolvNetPlus
Training & Education
Why Attend?
Synopsys is the world’s leading provider of solutions for designing and verifying advanced silicon chips. Join us at DVCon US 2026 to learn how we help customers optimize chips for power, performance, and cost, cutting months off their project schedules.
Lunch Panel Presentation
Generative AI: Is it Real or Merely a Hallucination?
Date & Time: Thursday, March 5, 2026 | 12:30 - 1:30 PM
Generative AI is reshaping the landscape of design and verification, but separating genuine breakthroughs from hype remains a challenge. As artificial intelligence becomes increasingly embedded in our daily workflows—from voice assistants to autonomous systems—the question arises: is generative AI delivering real, practical value in chip design verification, or are we chasing illusions? And, with the advent of Large Language Models (LLM) and Generative Pre-Trained Transformer (GPT) models, what are the possibilities in design verification?
This session will examine the current state of generative AI in design and verification. We’ll explore where Synopsys is investing in agentic solutions and what technology is being implemented in production environments by end users, delivering significant productivity boosts and automation. Join us to discover whether generative AI is truly revolutionizing the industry—or if it’s still more hallucination than reality.
Synopsys Sessions
Tutorial: System Validation - It's the Protocol Stupid
Presenters: Johannes Stahl (Synopsys), Rob Parris (Synopsys)
Date & Time: Monday, March 2nd | Time: 9:00 – 12:30PM
Abstract:
Today’s conventional wisdom is that you need the fastest and highest capacity verification engines to tackle the hardware and software complexity of complex multi-die systems. Those teams that are just thinking about these aspects are in for a rough awakening. Without a full range of protocol solutions matching the IP to their verification engines, they can spend months before they can run the 1st system validation test. Participants of this tutorial will learn what it takes to validate a protocol with state-of-the-art solutions.
In the first 90 minutes of the tutorial, we will highlight what state-of-the-art protocol solutions need to offer and how they are practically used.
In the second 90 minutes of the tutorial, we will pick selected protocol solutions and go deep into explaining what's inside. We will show practical examples that the audience will also be able to see in a live demo on the show floor.
Workshop: AI Meets Formal: Practical Applications from Industry Leaders
Presenters: Xiaolin Chen (Synopsys)
Date & Time: Monday, March 2nd | Time: 1:30 – 3:00PM
Abstract:
Formal verification offers unmatched rigor in ensuring design correctness, but its adoption is often hindered by steep learning curves, manual effort, and delayed integration into the design flow. This workshop explores how artificial intelligence (AI) is transforming formal verification into a more accessible, scalable, and efficient methodology from the earliest stages of development.
We will demonstrate how AI can intelligently guide assertion generation, property selection, and proof strategies—dramatically reducing setup time and increasing coverage. By learning from design patterns, verification history, and specification intent, AI enables earlier deployment of formal methods, improves usability for non-experts, and accelerates convergence for seasoned practitioners.
Through real-world examples and tool demonstrations, attendees will gain practical insights into AI-augmented formal verification workflows that deliver faster results, higher confidence, and reduced human effort. Whether you’re a verification engineer, formal expert, or RTL designer, this session will show how to harness AI to make formal easier to adopt and more impactful than ever before.
Workshop: Transforming Verification Debug: AI Innovations with Verdi
Presenters: Chun Chan (Synopsys)
Date & Time: Thursday, March 5th | Time: 1:30 – 3:00PM
Abstract:
This session highlights breakthrough AI-powered advancements in debug workflows for RTL design and verification, featuring state-of-the-art capabilities of the Synopsys Verdi platform. Attendees will learn how Verdi's intelligent technology leverages sophisticated artificial intelligence (AI) to enhance collaborative problem-solving, streamline data analysis, and facilitate multi-level debug across simulation, emulation, formal, and static verification environments. Integration with Synopsys verification tools and popular development environments enables users to interact with Verdi for a range of investigative and diagnostic tasks.
Through practical examples and a live demonstration, the session will showcase how next-generation AI can accelerate root cause analysis, suggest effective solutions, and enable comprehensive, data-driven debug strategies. Key features—including advanced interactivity, context-aware analysis, and innovative workflow integration—will be explored. Participants will see how Verdi platform's cutting-edge AI capabilities are transforming the debug process for modern silicon development.
Exhibit Booth
Visit Synopsys Booth #601
Stop by to see how we deliver comprehensive verification solutions spanning the complete design cycle, including simulation, emulation, advanced debug, static/formal verification, FPGA-based prototyping and virtual prototyping.