ASIP North America

ASIP Designer Virtual Seminar 2022

Join us for this virtual event to learn more about the power of application-specific instruction-set processors (ASIPs) and ASIP Designer

Wednesday, February 2, 9:00am - 11am PST

Extending RISC Processors into Flexible Accelerators using ASIP Designer

Case Studies in Artificial Intelligence and Image Signal Processing

The slow-down of Moore’s law and Dennard scaling has triggered an increased awareness of application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA.  ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product.  Maintaining a RISC-V ISA baseline facilitates compatibility with and reuse of existing processor ecosystem elements.

Synopsys’ ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP.  Using a unique compiler-in-the-loop and synthesis-in-the-loop methodology, the ISA and microarchitecture can be tuned quickly to the application domain.

This seminar introduces you to the ASIP Designer tool-suite.  It features two case studies from popular application domains.  The first case study, by the University of Virginia, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms, combining TVM and ASIP Designer.  Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations.  The second case study, by Synopsys, shows an accelerator for image signal processing.  A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.

Agenda | February 2, 2022

9:00am - 9:30am PST

An Introduction to Domain-Specific Processors, and ASIP Designer 

Patrick Verbist, Product Marketing Manager, Synopsys Belgium
Falco Munsche, Technical Marketing Manager, Synopsys Germany

Domain-specific processors (also referred to as Application-specific processors, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs, and will provide an overview of Synopsys' ASIP Designer tool suite. 


9:30am - 10:00 am PST

AI-RISC - Scalable RISC-V processor with tightly integrated AI accelerators and custom instruction extensions

Vaibhav Verma, PhD student at Electrical Engineering Department, University of Virginia
Mircea R. Stan, Virginia Microelectronics Consortium Professor, ECE Department, University of Virginia

Artificial intelligence (AI) accelerators are often specialized for a particular task, are very costly to produce, require special programming tools, and become obsolete as new AI algorithms are introduced. Hence, there is an urgent requirement for a system-level solution to streamline the integration of different AI accelerators into standard computing and programming stacks. We present AI-RISC as a solution to bridge this research gap. AI-RISC adopts a hardware/software codesign methodology where AI accelerators are integrated in the RISC-V processor pipeline at a fine-granularity and treated as regular functional units during the execution of instructions. AI-RISC also extends the RISC-V ISA with custom instructions which directly target these AI functional units (AFU) resulting in a tight integration of AI accelerators with the processor. AI-RISC adopts a 2-step compilation strategy where open-source TVM is used as the front-end compiler while Synopsys ASIP Designer is used as the back-end for complete SDK generation. AI-RISC provides 1.75x (MAC) to 17.63x (PIM VMM) performance improvement for a GEMV kernel and 1.41x (MAC) to 4.41x (PIM VMM) reduction in processor clock cycles for ResNet-8 neural network model from TinyMLPerf benchmark depending upon on the size of added accelerators and complexity of added instructions. 


10:00am - 11:00 am PST

Case study: Tmatch, a flexible stereo image matching accelerator designed with ASIP Designer (includes tool demonstrations) 

Falco Munsche, Technical Marketing Manager, Synopsys Germany

Stereo image matching algorithms are very demanding in respect of processing power (about 30 TMACs/s), requiring a huge number of Sum of Squared Difference (SSD) computations to calculate the pixel disparity. In this ASIP design, customized instructions and datapaths were added to a baseline RISC-V design in a stepwise approach. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop and synthesis-in-the-loop optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step. The resulting “Tmatch” design is a highly specialized vector ASIP with limited instruction level parallelism (ILP). It demonstrates a huge performance gain that cannot be achieved with a regular RISC-V processor with vector extensions.