ZeBu Scalable Debug Methodology

Scalable, Closed-Loop Debugging

Finding a hardware bug in the middle of a multi-billion-cycle test requires more than just dumping waveforms in and around an assertion or point of interest.  At the SoC system-level, full-chip waveform generation isn't practical—there's simply too much data.

Typical emulation tests may run for hours or days before a malfunction is observed, and the problem may be manifested anywhere within the billions of cycles of testing.  ZeBu's debug methodology leverages advanced technology at multiple levels of abstraction to help you converge on the relevant location and timing of an error:

  • Software debugger integration
  • Transaction logging and transactor packet/frame analyzers
  • Logic analyzers
  • SystemVerilog Assertions
  • Fast Waveform Capture

Once a failure has been isolated to a practical time window, ZeBu’s interactive Combinational Signal Analysis (iCSA) with native Verdi integration delivers on-the-fly, full signal waveform analysis.

Hardware debugging in a software context can be complicated by its asynchronous nature. When stepping through the embedded code in a software debugger, the processor continues to execute asynchronously, making it very difficult to exactly reproduce an intermittent problem. This can create an open-loop in debugging if you are unable to catch the failure on the first attempt.

ZeBu Post-Run Debug (zPRD) provides a deterministic framework to implement a closed-loop, reproducible debug environment. With zPRD, you can elect to rewind the test to any desired time, and perform new debugging tasks, such as waveform dumping, forcing signals, and updating memory contents. zPRD ensures that you never lose a bug once it's been discovered.