Software Innovation for Fast Emulation

Synopsys ZeBu Server is the industry’s fastest emulation system. ZeBu Server 4 delivers 2x higher performance over legacy emulation solutions, taking advantage of its unique Fast Emulation architecture, the most advanced commercial FPGAs, and innovations in FPGA-based emulation software. 

Every Synopsys Fast Emulation system is built on top of the most advanced compile and debug technologies developed specifically for FPGA-based emulation, including:

  • Fast Compile – Fast Compile technology supports parallel compile to enable fastest turn-around time for multiple turns per day. Fast Compile leverages standard multicore IT host infrastructure and offers more efficient runtimes especially for billion gate designs.
  • Unified Language Support – Fast Compile integrates the Synopsys Unified Compile with VCS front-end. Unified Compile is derived from the industry’s fastest simulation engine and eliminates costly discrepancies between semantic interpretation of the Verilog, SystemVerilog and VHDL input languages and allows for congruency between simulation, emulation, and prototyping models.
  • Performance Optimization – Fast Compile optimizes the run time performance of the user design based on its knowledge of the Fast Emulation system configuration, including the resources and communication paths available within each FPGA module and across modules. As the user locates their design to satisfy different requirements of capacity, performance and use cases, the backend of the compiler takes advantage of all aspects of the emulation hardware to generate the best possible performance.
  • 20-nm Silicon Place and Route Technology – Fast Compile includes support for emulation specific FPGA place and route algorithms, available only for Synopsys Fast Emulation, that enhances the market proven place and route engines provided by FPGA vendor tools. This modified place and route leads to highly predictable routing closure, optimizing compile time and highest performance across the FPGAs used for a particular design. 
  • Full Debug – Debug technology provides full visibility of essential signals, leveraging fast execution with at-speed notification of incorrect design behavior, the hierarchical, deterministic narrowing down of the debug window of interest, and the rapid creation of corresponding waveforms. This allows for the debug of billions of cycles without being limited by any fixed size data buffers. User visualization of waveform data is through the industry leading Verdi SoC debug environment.

These software innovations enable users with faster compile, advanced debug including native integration with Verdi, power analysis, simulation acceleration, and hybrid emulation. These use cases are further supported by industry’s most comprehensive suite of transactors, speed adaptors, and virtual models. 

Together, these layers deliver critical software innovations that drive the mainstream deployment of Fast Emulation use cases and the smooth integration of Fast Emulation systems within the Synopsys Verification Continuum.