Synopsys ZeBu Server is the industry’s fastest emulation system. ZeBu Server 4 delivers 2x higher performance over legacy emulation solutions, taking advantage of its unique Fast Emulation architecture, the most advanced commercial FPGAs, and innovations in FPGA-based emulation software.
Fast Emulation delivers the performance needed to make verification teams and software developers working on the most advanced chips successful. ZeBu Servers are modular, allowing users to deploy the capacity needed in a scalable and easily extensible fashion. ZeBu Servers enable users to tackle SoC verification tasks earlier, including:
- Software Bring-up – Early development and bring-up of embedded software applications on complex SoCs is a significant challenge driving the growing deployment of Fast Emulation. It allows running the actual software on the emulated full-chip SoC model, or in a Hybrid Emulation mode where a processor subsystem model is running the software on a host server, further accelerating the operating system boot. The most critical element in this use model is the ability to debug and validate correct interaction of the software with the hardware, facilitated through the support of common embedded software debuggers and the industry leading Verdi automated debug system for the hardware.
- Power Validation and Analysis – Includes power estimation and power validation. For power validation the user will validate that power domain on/off switching is executing correctly by compiling the design including IEEE 1801 UPF-defined power domain definitions for execution within ZeBu. Power analysis with ZeBu Power Analyzer provides the user with the ability to do software-driven power analysis starting with billions of cycles narrowing down power critical time windows. ZeBu Power Analyzer provides fast and accurate average and peak power estimations supporting millions of software workload cycles in power critical windows moving the power analysis earlier into the design cycle and with 1,000x faster turn-around time compared to traditional simulation-based methods. Finally, small windows around cycle power peaks are fed into the Synopsys PrimePower for signoff.
- Performance Validation – Allows the user to validate that the design is achieving its performance targets. With cycle accurate mapping of the RTL to the emulation system, the user can measure latencies on critical design paths and interfaces to insure software execution speeds are sufficient and mission critical deadlines are met.
- Simulation Acceleration – Through integration with the Synopsys VCS simulator, Fast Emulation enables the verification of block and platform level IP to be accelerated. Comprehensive testing using protocol specific Verification IP and the full visibility of the Verdi automated debug system maximizes your verification throughput.
Every Synopsys Fast Emulation system is built on top of the most advanced compile and debug technologies developed specifically for FPGA-based emulation. These software innovations enable users with faster compile, advanced debug including native integration with Verdi, power analysis, simulation acceleration, and hybrid emulation. These use cases are further supported by industry’s most comprehensive suite of transactors, speed adaptors, and virtual models.