Improving Robustness and Minimizing Over-Pessimism in the Face of Rising Design Variability – Part 1

While decreasing process nodes deliver huge benefits in terms of circuit density and increasing compute power, there is an associated downside — increasing design variability. This variability derives from the need for margin, the guard-banding of specifications that engineers introduce to improve design robustness and reduce tapeout risks. The tighter the specifications are set, the greater the risk of failure, impacting final costs. Designers need new tools to effectively and efficiently minimize the excessive design margins they specify, thereby reducing both cost and risk.

The first of this two-part post will explore the problems facing designers working on SoCs targeting energy-efficient design, and how Synopsys’ PrimeShield™ technology can help optimize designs for lower power while achieving aggressive time-to-market goals.

The Reality

Semiconductors have long been specified based on worst-case process, voltage and temperature (PVT). During the design phase, designers have had to balance performance against power and area (PPA), trying to achieve the needed performance-per-watt goals. To assess the impact of variability on circuit performance, designers resort to static timing analysis (STA) to assess each timing path. Due to the many factors that can impact PPA, designers often perform SPICE simulations to achieve more accurate results.

However, as both process nodes advance and circuit density increases, there is also increasing pressure on time to market. The result is that design teams are limited in the amount of robustness analysis they can perform pre-signoff, resulting in over pessimism (increasing design margins to ensure that performance and power targets are hit). It is a truism in design and manufacturing that the earlier mistakes can be caught, or optimizations performed, the cheaper the impact — robustness improvement is no exception.

The end result of this over design is decreased robustness that directly impacts the end-product PPA, time to market, and material costs — all factors that can make a semiconductor supplier uncompetitive in the marketplace. A robust statistical robustness analysis tool that can be applied earlier in the design cycle and help improve design immunity to variation is needed.  

Enter PrimeShield

Monte Carlo on Steroids

While Monte-Carlo SPICE simulation has been the gold standard for circuit analysis, it does not scale for today's circuit densities. By their very nature, Monte Carlo simulations must repeat the same analysis thousands, or even millions of times for high-sigma accuracy, making it practical for only dozens of cells. 

PrimeShield leverages Synopsys’ PrimeTime® golden signoff engine to perform SPICE-accurate timing calculations and variation modeling in seconds. To achieve the needed throughput, PrimeShield takes advantage of the repetitive nature of Monte-Carlo analysis and uses patented machine-learning technology to greatly improve analysis performance. The result is a 100 to 10,000 times improvement in analysis throughput, performing statistical simulation on critical timing paths in large-scale SoCs with billions of cells within minutes versus days or weeks as required by traditional statistical simulations. 

Analog engineer thinking about layout effeciency

PrimeShield for Low-Power Design

PrimeTime introduced advanced voltage scaling technology that enabled designers to perform accurate analysis at any voltage level within a broad range. Designers now had a way to sweep through the voltage range, trial-running the same design at various voltage levels, and eventually, finding a voltage sweet-spot for the desired PPA or performance-per-watt targets. While the PrimeTime solution has proven to be both accurate and effective, the sweeping process is both time and resource consuming.

PrimeShield has expanded on the PrimeTime core technology and introduced a new PPA signoff analysis type called voltage slack which represents the minimum voltage per-cell or per-path for a design to meet performance requirements. This signoff analysis enables designers to efficiently pinpoint voltage bottlenecks to improve IR-drop robustness, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages directly. Variable voltage is now available as a PPA optimization metric. 

Analog engineer thinking about layout effeciency

The magnitude of voltage slack determines sensitivity of the path to voltage change. Paths with small voltage slack are considered operating voltage critical. PrimeShield prioritizes fixing paths with smaller voltage slacks to improve design resilience to IR drops. It also enables power saving by pushing down the operating voltage or frequency boost by raising the operating voltage. In addition, PrimeShield enables voltage-slack-based optimization and has been found to be highly beneficial for mixed VT designs.

Dynamic or switching power has become a top focus for power optimization, especially for advanced-node HPC applications. While lowering the operating voltage can directly reduce dynamic power, operating voltage has long been a static metric in design flows. The higher cell and power density at advanced nodes also makes any reduction to voltage supply levels an extremely difficult task. Despite this, lower voltage levels can be essential to achieve competitive performance-per-watt goals. As a consequence, a new PPA opportunity has emerged for power.

Power is related to voltage, but lowering operating voltage impacts performance. PrimeShield computes the lowest operating voltage required by each path to meet timing, accurately accounting for voltage slack. Using this data, PrimeShield performs a voltage robustness analysis to identify bottleneck cells with large IR-drop sensitivity and inadequate pin slack. As a result, designers can fine-tune a design to achieve the lowest operating voltage while hitting performance targets.

Analog engineer thinking about layout effeciency

Thus, PrimeShield voltage slack and robustness analysis enables users to improve design resilience to voltage variation in ultra-low power design and also drive additional power savings for the best energy efficiency.

Part 2 of this post explores how PrimeShield can help SoC designers optimize their designs for high performance while meeting aggressive design schedules, as well as provide some real-world examples.