Semiconductors have long been specified based on worst-case process, voltage and temperature (PVT). During the design phase, designers have had to balance performance against power and area (PPA), trying to achieve the needed performance-per-watt goals. To assess the impact of variability on circuit performance, designers resort to static timing analysis (STA) to assess each timing path. Due to the many factors that can impact PPA, designers often perform SPICE simulations to achieve more accurate results.
However, as both process nodes advance and circuit density increases, there is also increasing pressure on time to market. The result is that design teams are limited in the amount of robustness analysis they can perform pre-signoff, resulting in over pessimism (increasing design margins to ensure that performance and power targets are hit). It is a truism in design and manufacturing that the earlier mistakes can be caught, or optimizations performed, the cheaper the impact — robustness improvement is no exception.
The end result of this over design is decreased robustness that directly impacts the end-product PPA, time to market, and material costs — all factors that can make a semiconductor supplier uncompetitive in the marketplace. A robust statistical robustness analysis tool that can be applied earlier in the design cycle and help improve design immunity to variation is needed.