Programmable Electrical Rules Checking (PERC) is a method for checking reliability issues of integrated circuit (IC) designs that cannot be checked with design rule checking (DRC) or layout versus schematic (LVS). These reliability checks are frequently electrostatic discharge (ESD) related, but they can extend to other checks as well, including electrical overstress (EOS), dielectric breakdown, etc. These rules involve connectivity and netlist information, but also need to support full customization from design to design, which is enabled by the programmable aspect.

PERC checks fall into 4 major categories:

  • Netlist Checks. Checks that can be done entirely on a netlist; no layout data is necessary.
  • Netlist Driven Layout Checks. Checks that are done on the layout, but a preceding analysis of a netlist is done to determine the area of interest for the layout check.
  • Current Density Checks. Checks done on the layout to determine the current carrying capability of the layout in the ESD discharge path.
  • Point-to-Point (P2P) Resistance Checks. Checks done on the layout to determine the resistance of the ESD discharge path, to verify that it is low resistance ensuring the current will choose that path

How Does PERC Work?

Because there are 4 types of checks, there are different data flows depending on the check. The most fundamental piece in PERC is the “Netlist Analysis Engine.” The module runs first in all flow, and it is the programmable piece giving the name PERC. In this stage, a netlist is read in and analyzed for anything that a customer may want to know about their netlist. That can result in errors being reported or feed subsequent modules, depending on the type of check.

This is illustrated below with a simple block diagram:

PERC Block Diagram | Synopsys

If the netlist to be analyzed is from the layout, the LVS Extract will need to be run to produce that netlist, although that step is not shown above. LVS Compare is not used in these PERC flows.

Common PERC Applications

Because PERC is a programmable solution, it has broad usage and applications. Anything a designer wants to know about a netlist and the corresponding shapes can be programmed.

There are a number of ways to partition the problem space. The most common is between ESD and non-ESD applications.

ESD applications do represent a significant percentage of PERC usage. For ESD checking, all 4 types of checks (netlist, netlist driven layout, current density and point to point resistance) come into play. The netlist checks confirm the existence of the ESD protection circuitry and can be run on the schematic or the extracted layout netlist. The netlist driven layout, current density and point to point resistance all require layout. Current density and point to point resistance also leverage StarRC for the R-extraction.

PERC Diagram 2 | Synopsys

Non-ESD applications tend to fail into the category of “methodology checks.” This is a broad catch-all type phrase to signify that customer use PERC type checking to do a wide spectrum of other analysis. In the category of netlist checks, this can include: 

  • EOS (electrical overstress)
  • Floating gate
  • Level shifter placement
  • Fanout
  • Leakage
  • Netlist statistical analysis

In the netlist driven layout checks, the most common non-ESD application is voltage dependent spacing, but it can also be used for geometric symmetry checking and other applications. Current density and point-to-point resistance are almost entirely used for ESD, and so no additional application is mentioned here.

What Solutions Does Synopsys Offer?

Synopsys’ IC Validator physical verification is a comprehensive signoff solution, including design rule checking (DRC), layout versus schematic (LVS), fill capabilities and more.

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