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Table of Contents
Definition
Layout Versus Schematic (LVS) checking compares the extracted netlist from the layout to the original schematic netlist to determine if they match. The comparison check is considered clean if all the devices and nets of the schematic match the devices and the nets of the layout. Optionally, the device properties can also be compared to determine if they match within a certain tolerance. When properties are compared, all the properties must match as well to achieve a clean comparison.
How Does LVS Work?
Two main processes make up the LVS flow. The first process in the flow is extraction, in which the layers within the layout database are analyzed and all the devices and nets are extracted. The second process in the flow is compare, in which the actual comparison of devices and nets occurs.
The LVS runset contains a series of function calls that control both extraction and netlist comparison.
Common LVS Issues
LVS errors can be classified into two main categories:
Extraction Errors
- Text short and open
- Device extraction error
- Missing device terminal
- Extra device terminal
- Unused text
- Duplicate structure placement
Compare Errors
- Unmatched nets in the layout/schematic
- Unmatched devices in the layout/schematic
- Property errors
- Port swap errors
What Solutions Does Synopsys Offer?
Synopsys’ IC Validator physical verification is a comprehensive signoff solution, including design rule checking (DRC), layout versus schematic (LVS), fill capabilities and more.
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