11:15 a.m. - 12:00 p.m. CEST
Stewart Williams, Senior Automotive Vertical Marketing Manager, Design Group, Synopsys
Description: The ISO 26262 standard defines functional safety (FuSa) requirements to achieve the target automotive safety integrity level (ASIL) for applications such as autonomous driving and advanced driver assistance systems (ADAS). Key objectives for an automotive SoC design project are to optimize power-performance-area (PPA) in the presence of safety mechanisms and reduce overall effort and impact on the development schedule. Synopsys’ comprehensive automotive design flow provides a unified FuSa verification solution with automated FMEA and FMEDA, early functional safety analysis, and a unified fault campaign for measured FMEDA to confirm that target ASIL is met. Synopsys’ new native RTL-to-GDSII solution, driven by FuSa intent, insures that safety mechanisms are implemented per design specification. This presentation describes the comprehensive automotive design flow and an example based on a Synopsys ARC functional safety processor.
Speaker: Stewart Williams is Senior Automotive Vertical Marketing Manager in the Design Group at Synopsys where he leads the automotive solutions encompassing Digital Implementation, Test, Signoff, and Custom Design. Prior to his current role, Stewart was Senior Technical Marketing Manager for Synopsys’ flagship place & route product. Before joining Synopsys, he managed the product engineering team for parasitic extraction at Cadence Design Systems. Stewart received his bachelor’s degree in Electrical Engineering from Virginia Tech in 1993, and M.S. and Ph.D. degrees in Electrical and Computer Engineering from North Carolina State University in 1995 and 1999, respectively.
12:00 p.m. - 12:20 p.m. CEST
Frank Nolting, Applications Engineer, Design Group, Synopsys
Description: Automotive systems have stringent functional safety requirements as defined by the ISO 26262 standard. To meet the target Automotive Safety Integrity Level (ASIL), designers face the challenge on how many redundant structures to add with minimum area and cost penalty. Another challenge is completing the assessment late as it leaves too little time to make changes to the design. This presentation will show how Synopsys TestMAX FuSa uses static analysis early in the design flow either at RTL or Gate netlist to calculate ISO 26262 metrics such as Single Point Fault Metric (SPFM) and Diagnostic Coverage. TestMAX FuSa identifies modules in the design that have the highest probability of causing functional safety failures and provides guidance to achieve the target ASIL.
Speaker: Frank Nolting studied at the Technical University of Kaiserslautern in Germany and graduated with a master degree in electrical engineering and computer science. Frank worked at Infineon before he joined Synopsys in 2001. Since then he supports all Synopsys DFT tools as an Applications Engineer.
11:15 a.m. - 12:15 p.m. CEST
Dave Reed, Senior Director, Design Group, Synopsys
Description: This presentation will introduce several novel analog design and layout productivity innovations in Custom Compiler that Synopsys uses to deliver 100’s of analog and mixed-signal IPs each year. Traditional analog design flows don’t provide required automation and productivity gain especially when compared to the advances made for digital SoC design. On the other hand, the effort needed to develop and close analog layout has increased significantly because of challenges like variability, and design rule complexity, impact of parasitics, reliability requirements, etc. Synopsys Custom Compiler accelerates the creation of analog layout through innovations in custom layout automation and integrates industry standard analysis and signoff capabilities to drive rapid design closure. We will demonstrate how Custom Compiler’s visually-assisted layout automation tightens communication between design and layout teams and reduces overall layout time. We will also show how Custom Compiler’s Extraction Fusion technology with StarRC enables designers to extract parasitics from partially completed layout – without needing to finish the design and run LVS.
Speaker: Dave Reed is Senior Director of Custom Design Product management at Synopsys. He has been involved in IC design and electronic design automation for more than 35 years, with a focus on analog and custom design. Prior to Synopsys Dave was co-founder and CEO of Blaze DFM, which helped engineers overcome design challenges of advanced process nodes.
9:30 a.m. - 10:00 a.m. CEST
Dineshkumar Selvaraj, Infineon Technologies AG
Description: This paper presents the usage and benefits of Virtual Prototyping (VP) for Embedded Software Development on the Infineon AURIX™ range of devices. The objective is to show the unique value of AURIX™ Virtual Prototypes for both pre and post silicon development and to give an insight into the long collaboration between Infineon and Synopsys in bringing differentiated Virtual Platforms to the market. The case study will examine safe and secure vehicle application development, from current to next generation. We will show how Infineon uses the Virtual Prototype internally to shift left software development and testing. We will also look at how continuous integration (CI) increases the efficiency of functional safety testing.
Speaker: Dinesh is currently leading the Virtual prototype development of AURIX family of Microcontrollers in Infineon Technologies. He has got 15+ years of experience in ESL domain with focus into development of VP for classical pre silicon SW validation, RTL co-simulation and also early performance analysis and optimization using models. Prior to Infineon, he worked with Intel and Tata Elxsi. He pursued electrical engineering from NIT, Trichy.
10:00 a.m. - 10:30 a.m. CEST
Matthias Glück, Volkswagen AG
Description: Functional Safety (FuSa) is a key requirement of automotive systems. Especially highly available systems like Electronic Power Steering (EPS), where malfunctions can lead to life threating events, are governed by the highest Automotive Safety Integrity Level D (ASIL-D) as defined by ISO 26262. In order to bring down the cost, the EPS development and test department at VW is shifting towards a virtual testing strategy using a virtual Hardware ECUs based on Synopsys Virtualizer. We leverage the fault injection capabilities to trigger safety critical fault conditions and thus increase the coverage of the control Software. We are working on moving the software tests to a virtualized environment on a server farm, including state-of-the-art software engineering methods like continuous testing and continuous integration. In our presentation we will also share our experiences with the ASIL qualification process for ASIL D compliancy as well as mapping the original safety tests to the virtual Hardware ECU.
Speaker: Matthias is the technical lead for Testing Methodology and Strategy of Electric Power Steering systems at Volkswagen. He is also a member of the company-wide boards on test strategy and on virtual Hardware ECUs. Before joining Volkswagen in 2014, Matthias has worked for 11 years at Intel as a Senior Component Design Engineer in various testing and test methodology roles worldwide, e.g. for cyber security, hardware virtualization and supercomputing. Matthias holds a diploma degree in Electrical Engineering from Technical University Berlin.
9:30 a.m. - 10:30 a.m. CEST
Anand Thiruvengadam, Senior Manager, Design Group, Synopsys
Description: The increased need for safety, low defect rate, and long-term reliability is driving automotive IC designers to augment expert judgement with fault simulation to analyze the impact of random hardware defects on design safety and reliability and ensure compliance with ISO 26262 requirements. This tutorial provides an overview of how Synopsys TestMAX CustomFault can be used to accelerate block-/IP-level functional safety and test coverage, and enable SoC-level FMEDA analysis in conjunction with Synopsys Unified Functional Safety solution.
Senior Manager, Design Group, Synopsys
Speaker: Anand Thiruvengadam, a Senior Manager in the Design Group at Synopsys, is responsible for circuit simulation product marketing. Anand has 15+ years of combined experience in high technology product management and product development. Prior to Synopsys, he worked at PriceWaterhouseCoopers (PwC) as a management consultant, focusing on strategic and operational transformation initiatives for various enterprises in the consumer electronics, networking, storage, enterprise software, and semiconductor industries. Prior to PwC, Anand worked at AMD and Alliance Semiconductor, where he successfully led the design and development of high performance Analog, PMIC, and Memory products. Anand has an M.B.A. from the Haas School of Business at University of California, Berkeley, and an M.S in Electrical Engineering from Oklahoma State University.
10:30 a.m. - 10:45 a.m. CEST
Gernot Koch, CAD Manager, TDK-Micronas GmbH
Description: In our presentation, we will talk about application areas for analog fault simulation, it's challenges and compare a few different approaches used in the commercially available tools. We explain how we apply CustomFault to determine ISO 26262 metrics required as input to FMEDA, the challenges this presents, and how we partnered with Synopsys to resolve these challenges. We close with a few illustrating examples.
Speaker: Gernot Koch holds a Master in Computer Science from Karlsruhe Institute of Technology (KIT) 1993 and a Doctorate in Computer Science from University of Tübingen, 1998. He spent 5 years developing EDA tools in California (Synopsys, Bridges2Silicon). He "Switched sides" in 2003, and became a CAD engineer at Micronas (now TDK-Micronas), specializing in System Level Design, analog and digital verification, and PDKs. Managing CAD team at TDK-Micronas since 2009.
11:15 a.m. - 12:15 p.m. CEST
Farzin Rasteh, Sr Mgr. Applications Engineer, Design Group, Synopsys
Description: The Mixed-Signal Verification solution from Synopsys offers a variety of features and techniques to develop smart testbenches that check the behavior of both the analog and digital parts of a design, and provides capabilities to significantly shorten the simulation run times and improve test coverage. In this session we review some of the key features in Synopsys’s Mixed-Signal solution that allow those capabilities.
Speaker: Farzin Rasteh is the senior Application Engineering Manager for Analog and Mixed-Signal Verification at Synopsys. He is an Electrical Engineer with experience in signal integrity, RF, and analog IC design, as well as ASIC design and verification, and emulation. For more than 10 years Farzin has been managing the support and methodology development for Analog and Mixed-Signal verification tools at Synopsys . Farzin has a Bachelor’s degree in Electrical Engineering from Sharif University of Technology in Iran, and Master’s degree in Information Technology from Carleton University, Canada.