Synopsys UCIe IP Solutions

Synopsys’ complete Universal Chiplet Interconnect Express (UCIe) IP solution includes controller, PHY and verification IP. The PHY is available in advanced FinFET processes and offers high-bandwidth, low-power and low-latency die-to-die connectivity in a package. The PHY’s flexible architecture supports standard and advanced packaging technologies, delivering up to 4Tbps bandwidth in a multi-module configuration. Synopsys UCIe Controller IP supports widely used protocols such as PCI Express and CXL and enables latency-optimized NoC-to-NoC links with streaming protocols. Synopsys UCIe Controller and PHY IP solutions enable robust and reliable die-to-die links with testability features for known good dies and CRC or parity checks for error correction.

Contact us for more information and to discuss your multi-die SoC needs.

Synopsys UCIe Controller IP Datasheet
Synopsys UCIe PHY IP Datasheet

 

Highlights
  • UCIe Controller
    • Low Latency controller for UCIe-based die-to-die connectivity
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports Streaming, CXL and PCIe protocols
    • Error detection and correction with optional CRC and retry functionality
    • Supports single module and multimodule UCIe configurations
    • Enables low latency NoC-to-NoC interface between two dies
  • UCIe PHY
    • Delivers up to 4Tbps with up to 5.2Tbps/mm of die edge
    • High-bandwidth, low-power, low-latency multi-module PHY for applications requiring reliable connections between dies within a package
    • Supports advanced packaging technologies such as silicon interposer, silicon bridge or RDL fanout
    • Supports standard packaging technologies such as organic substrate or laminate