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Overview
The UCIe™ (Universal Chiplet Interconnect Express™) released the UCIe 2.0 specification to bring efficient and scalable chiplet interconnection to the forefront of multi-die technology. In this blog we will discuss the best way to ascertain that chiplets are interoperable, and how to manage bring-up, initialization, discovery, events and messages, security and access control, as well as debug and test.
Before we dig deeper into UCIe 2.0, let us revisit the UCIe 1.1 specification that added features to cater to different application segments. (You can refer to our previous blog on UCIe 1.0 / UCIe 1.1 verification solution to understand our modular architecture for multi-chiplet verification.)
UCIe 1.1 Features
Flit mode support for streaming protocol
Benefits
Effective way for agnostic transport of any protocol
CRC and retry support for streaming mode
Enable error free transmission at UCIe transport, move burden away from higher layer
Stack mux on die-to-die adapter with options of two different protocols on multiplexer
Effective utilization of link bandwidth and flexibility for mix-match of protocols based on system needs
Multi module link mode
Clarifications and detailed semantics of multi-module operation
UCIe 2.0 - Enabling Interoperability
While the UCIe 1.1 specification revision focused on key extensions for multi-vendor heterogenous systems, UCIe 2.0 is sowing seeds to define a chiplet interoperability ecosystem stack with a “System Architecture” definition, introducing provisioning manageability of System-in-Package (SiP).
Let’s explore the new features in UCIe 2.0.
- Management Transport Protocol (MTP): MTP enables communication between management entities within a SiP management network. Management entities on this network generate and receive UCIe management transport packets, which traverse the network without modification. UCIe Memory Access protocol (UMAP) enables read and write access to memory associated with management entities with ability for access control.
- UCIe Debug and Test Architecture (UDA): UDA is architected for chiplet-level and SiP-level testing and debug. UDA uses functional sideband and/or mainband link and a functional management network for test and debug purposes.
- UCIe-S Sideband only (SO) port: SO port is permitted for test/manageability purpose in a standard package. It is meant as an option for a low-speed test port that one can use at TestChip level.
- x8, x4 (degraded) link width support for standard package: Capability for x8 (degraded x4) pin module is enabled for standard packages, whereas version 1.1 only supported x16 and x64 physical layer interfaces.
- UCIe 3D packaging: 3D packaging techniques enable chiplets to be stacked vertically. This method not only boosts performance and reduces latency but also enhances power efficiency, addressing the crucial needs of modern semiconductor designs. By adhering to UCIe standards, 3D packaging enables more compact, high-performance chip designs that can meet the demands of future applications.
In addition to Interoperability, UCIe 2.0 is paving way for defining scalable verification and validation platforms for chiplet designs.
Synopsys UCIe End-to-End Verification and Validation Solutions
Synopsys is a contributing member to the UCIe specification committee and is working closely with industry leaders to support features and use cases for the UCIe 2.0 specification in Synopsys Verification IP (VIP) for UCIe 2.0.
Synopsys’ complete UCIe IP solution includes controller, PHY, and VIP. Synopsys UCIe controller and PHY IP solutions enable robust and reliable die-to-die links with testability features for known good dies. The IP, operating at maximum data rates, supports standard and advanced packaging technologies and has achieve multiple silicon successes across foundry process and packaging technologies.
Synopsys UCIe 2.0 VIP, functional test suites, and protocol solutions for hardware-assisted verification platforms, ZeBu, and HAPS, leverage close collaboration with Synopsys’ industry leading IP portfolio to enable the highest quality verification and validation collateral for our customers.
Synopsys silicon proven IPs are verified using independently developed Synopsys VIPs, providing companies with an industry leading UCIe solution. Synopsys SoC verification kit solutions provide ready to go IP bring-up and sanity setup with IP-VIP or IP-Solutions integrations and collaterals, saving at least 50% of time and resources spent in bringing IP up in the SoC Verification environment. With pre-verified components and ready-to-use testbenches Synopsys VIP accelerates the development cycle, reducing time-to-market.
Because the target usage for UCIe is die-to-die interconnects, the payload that the chiplet RTL requires demands faster hardware-based pre-silicon solutions. Synopsys transactors based on Synopsys IP enable fast verification hardware solutions including Synopsys ZeBu® emulation systems and Synopsys HAPS® prototyping systems for validation use-cases.
Synopsys protocol verification solutions are natively integrated with the Synopsys Verification Family of products, including Synopsys Verdi® debug and regression management and automation with Synopsys VC Execution Manager.
Conclusion
The industry is rapidly deploying multi-die designs, requiring the technology to rapidly evolve in order to meet demand. UCIe 2.0 is the next step to enable a chiplet interoperability ecosystem. Synopsys is a leader in multi-die, contributing to the UCIe specificiation committee and providing a complete UCIe IP solution.
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