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Key IP Requirements for 3D Integration and UCIe in AI Chips

Date: Mar 27, 2025 | 10:00 AM PDT

Featured Speaker:

  • Manuel Mota Sr. Product Manager, Synopsys

 

Why you should attend:

High-bandwidth die-to-die connectivity for AI workloads and new 2.5D and 3D packaging options are driving unique IP requirements and new architectures.  Designers must consider cost and performance tradeoffs when selecting packaging technologies and determining die stacking options.

Learn more about:

  • Drivers for high-bandwidth UCIe IP at 40G data rates and beyond  
  • New IP requirements for 3D integration 
  • Implications of die stacking options, such as face-to-face or face-to-back configurations 
  • Proof points showing the UCIe variants for organic substrate, high-density advanced, and 3D packaging technologies 

Register Now

Featured Speaker

Manuel Mota
Sr. Product Manager, Synopsys
Manuel is responsible for the die-to-die interface IP product line. Previously he led product management roles focusing on SerDes interfaces, and analog/digital converters. Manuel has focused on enabling the industry’s evolution towards multi-die designs by authoring multiple technical papers on the subject.