SNUG Penang Call for Papers

Call for Papers is Now Open

If you have used Synopsys technology to overcome difficult design issues and to accelerate your innovation, the SNUG community wants to hear from you!  

Share your experience using Synopsys tools and IP at the 2018 Synopsys Users Group (SNUG), Penang.   SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.

As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you’ll be eligible for significant cash awards.

For more information, please review the Guidelines or contact your SNUG Team.

The call for papers is open February 28 – April 16, 2018. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by April 30, 2018.

We have a preliminary list of topics to get you started, but don’t let that limit your ideas or innovation in your submission.

  • Accelerating Timing, Leakage & Functional ECOs
  • Accelerating Verification (Simulation, Debug, Coverage, Verification IP, SoC Verification, Low Power, Formal and Static)
  • Advanced Application Methodologies (Arm, Automotive, Graphics/GPUs, Processors)
  • Applying Advanced Technologies (16nm and below, 3DIC, FinFET)
  • Characterization (Standard Cell, Memory, I/Os, Complex Cells)
  • Design Closure and IC Signoff (DRC/LVS, STA, Extraction)
  • High Performance, Low Power, Area Optimization Design Methodologies
  • Emulation and Prototyping (Virtual Prototyping, HAPS, Hybrid Prototyping)
  • FPGA Design and Verification
  • Full Custom Design Flows
  • Maximizing Results with Established Technology Nodes (20nm and above)
  • System Design, Hardware/Software Integration, and Validation 
  • Transistor-level and Analog/Mixed-Signal Verification (SPICE, FastSPICE)
  • Design and Verification Debug (RTL/Gates, Testbench, UVM, Protocol, UPF, Hardware/Software)
  • Functional Safety Verification (Fault Modeling, Fault Simulation) 
  • IP Integration into SoCs (Interfaces, Processors, Security, Foundation IP, etc.) 
  • Low Power Design (Analysis and Power Reduction Methodologies and Techniques, Static and Dynamic Low Power Verification) 
  • Maximizing Results with Established Technology Nodes 
  • Static and Formal Verification (Advanced Linting, Clock and Reset Domain Verification, Timing Exception Verification, Formal Property Verification, Formal Apps) 
  • Test Automation (Design-for-Test (DFT), Yield Analysis, ATPG, Diagnostics, Compression) 
  • Your own great idea!

Copyright Statement

Please carefully read the following notice before submitting your written materials to the SNUG program.

By submitting materials to the SNUG program, you and your employer are giving Synopsys the following rights: to reproduce, publish and distribute the submitted materials on the SNUG web site for access by Synopsys employees, contractors, and licensees.

It is your responsibility to confirm that your employer agrees to the use described above. You and your employer reserve the right to modify the submitted materials at any time. Synopsys shall reproduce any copyright or other legal notices that you include in your submitted materials. Synopsys will not use your submitted materials for product marketing purposes without first obtaining your express written consent.

If you have any questions about this copyright statement, please contact the SNUG Team before submitting your proposal.

For the complete author submission timeline, please view the SNUG Penang Author’s Kit.

If you have questions, please contact the SNUG Team.