Share your experience using Synopsys tools and IP at the 2017 Synopsys Users Group (SNUG), Penang. SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.
As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you’ll be eligible for significant cash awards.
For more information, please review the Guidelines or contact your SNUG Team
The call for papers is open February 22 – March 27, 2017. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by April 17, 2017.
We have a preliminary list of topics to get you started. But, don’t let that limit your ideas or innovation in your submission.
- Accelerating Functional ECOs
- Accelerating SoC Verification (Verification Planning & Coverage, Analog-Mixed Signal, UVM Verification)
- Advanced Application Methodologies (ARM, Graphics/GPUs, Processors)
- Advanced Design Methodologies (High Performance, Low Power, Area Optimization, Time to Market)
- Analog and Mixed-Signal Simulation (SPICE, FastSPICE)
- Applying Advanced Technologies (7/10/14/16nm, 3DIC, FinFET)
- Characterization (Standard Cell, Memory, I/Os, Complex Cells)
- Design and Verification Debug (RTL/Gates, Testbench, UVM, Protocol, UPF, Hardware/Software)
- Design Closure and IC Signoff (DRC/LVS, STA, Extraction)
- FPGA Design and Verification
- Full Custom Design and Methodologies
- Functional Safety Verification (Fault Modeling, Fault Simulation)
- IP Integration into SoCs (Interfaces, Processors, Security, Foundation IP, etc.)
- Low Power Design (Analysis and Power Reduction Methodologies and Techniques, Static and Dynamic Low Power Verification)
- Maximizing Results with Established Technology Nodes
- Prototyping (Virtual Prototyping, HAPS, Hybrid Prototyping)
- Static and Formal Verification (Advanced Linting, Clock and Reset Domain Verification, Timing Exception Verification, Formal Property Verification, Formal Apps)
- System Design and Validation
- Test Automation (Design-for-Test (DFT), Yield Analysis, ATPG, Diagnostics, Compression)