SNUG Penang Call for Papers

Share your experience using Synopsys tools and IP at the 2019 Synopsys Users Group (SNUG), Penang.   SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.

As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you’ll be eligible for significant cash awards.

For more information, please review the Guidelines or contact your SNUG Team.

The call for papers is open February 26 - April 15, 2019. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by May 6, 2019.

We have a preliminary list of topics to get you started, but don’t let that limit your ideas or innovation in your submission.

AI and Machine Learning

• Improving productivity and achieving faster QoR closure with machine learning in the Synopsys design flow
• From the data center to the edge – enabling highest performance AI designs with Synopsys implementation solution
• AI architecture exploration and validation with virtual prototyping
• Formal datapath verification and early software development and validation using emulation for AI processors
• Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications

Automotive

• Best practice on how to use a Synopsys digital implementation flow to build automotive SoC with functional safety requirements like redundancy (TMR, dual core lock step, ...) 
• Accelerate automotive software development and validation with virtual prototyping
• Complete functional safety verification solution with formal and static verification, and industry-leading fault simulation
• Unique semiconductor-focused FMEA/FMEDA automation
• Implementing safety critical designs for automotive applications
• Designing ISO 26262 required In-System Test using Synopsys tools
• High reliability design techniques for automotive designs
• Accelerating ISO 26262 certification with ASIL ready certified IP

Analog Mixed Signal Simulation

• Application of Monte Carlo analysis to improve AMS circuit robustness with HSPICE, FineSim or CustomSim
• How to minimize design margin with accurate reliability analyses including heat-aware EM, IR and device aging with CustomSim, FineSim or HSPICE
• Best practices in mixed-signal verification with advanced digital verification methodology with CustomSim and VCS
• How to verify power and signal integrity for multi-gigabit circuits with HSPICE
• Application of CustomSim circuit check to find electrical rule violations in circuits

Custom Implementation

• Productivity gain from using Custom Compiler Template Assistants (Symbolic Editor)
• Productivity gain from using Custom Compiler In-Design Assistants (DRD, EM/IR, RCx)
• Productivity gain from using Custom Compiler’s Co-Design with IC Compiler II
• Robust analog design from using Custom Compiler and SAE (Simulation Analysis Environment)

Design PPA, TTR Optimization and Signoff

• Optimal design flow for digital implementation of advanced node designs
• Accelerating turnaround time for large designs with Design Compiler Graphical and IC Compiler II
• How to achieve best Performance, Power and Area for Arm CPUs
• Using parallel processing to accelerate physical and full chip timing signoff
• Accelerating full chip TAT for large designs using IC Validator physical signoff
• Optimization techniques for low-power IoT designs
• Early time-based peak power analysis with PrimePower with RTL-based vectors
• Using physical-aware ECO capabilities to improve PPA and accelerate timing closure
• Achieving reliable and implementation ready macro placement QoR using the latest IC Compiler II macro placement technologies
• Using RedHawk Fusion to improve IR and EM targets for better power grid and design reliability

FPGA Synthesis

• Accelerate FPGA design and validation utilizing the FPGA platform
• Advanced debug for faster design completion 
• Optimizing FPGA design for best area and performance 
• Complete functional safety design automation for FPGA based applications

Silicon Test and Yield Analysis

• Success with early RTL analysis, physically-aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
• Highlighted applications include automotive, mobile, and processors

SoC Verification

• Improving simulation throughput with fine-grained parallelism (FGP)
• Best practices for estimation and verification of low power designs
• Verification of system performance on a SoC or subsystem
• Faster and better convergence using formal methods
• Best practices for verification coverage planning and closure
• Verification of system performance on a SoC or subsystem with fast emulation
• Best practices for implementing CDC/RDC sign-off
• Improving productivity using advanced debug techniques (including AMS and HW/SW debug)
• Best practices for implementing verification IP (VIP)

Software Bring-up

• Accelerating software bring-up with emulation and prototyping
• Improving software-driven hardware verification with hybrid-emulation
• Using FPGA-based prototyping to accelerate system validation of IP and SoCs
• Accelerating software development with virtual prototyping

Successful IP Integration into SoCs

• Interface IP such as USB, PCI Express, DDR, MIPI, Ethernet, Multi-Protocol SerDes, etc.
• Embedded ARC processors & embedded vision processors
• OTP non-volatile memory, memory compilers & logic libraries
• Integration of IP into cloud computing SoC designs
• Integration of IP on advanced FinFET designs