Call for Content Info

Call for Content is open. If you have used Synopsys technology to overcome difficult design issues and to accelerate your innovation, the SNUG community wants to hear from you! Share your experience using Synopsys tools and IP at SNUG Korea, Synopsys Users Group (SNUG),  July 10, 2024


For over three decades, SNUG has connected users and technical experts to network and share best practices for tackling design and verification challenges. This past year was a major pivot in how all of us live, work, and connect to each other. As a SNUG presenter, you will increase your visibility in the Synopsys user community. In addition to the professional recognition, you will be eligible for awards (please check your company’s gift acceptance policy).

The call for content is open. The SNUG Team will review the submitted proposals & notify presenters of preliminary program acceptance on May 20, 2024.


We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation:


  • Improving productivity and achieving faster QoR closure with machine learning in the Synopsys design flow
  • From the data center to the edge – enabling highest performance AI designs with Synopsys implementation solution
  • Architecture exploration and early software development with virtual/physical prototyping
  • Formal verification of datapath designs
  • Using emulation for AI software stack validation
  • AI-enabled productivity and performance innovation
  • Using virtual test environments for network system validation
  • Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications
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  • Accelerate automotive software development and validation with virtual prototyping
  • Complete functional safety verification with industry-leading fault simulation, formal and static verification
  • High reliability design techniques for automotive designs
  • Hardware security verification
  • Implementing safety critical designs for automotive applications
  • Designing ISO 26262 required In-System Test using Synopsys tools
  • Accelerating ISO 26262 certification with ASIL Ready Certified IP
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  • Addressing analog, custom digital or memory design verification TAT bottlenecks with heterogenous compute acceleration
  • RF analysis of RFIC or analog periodic circuits using FineSim
  • Ensuring AMS design robustness with advanced variability analysis
  • Minimizing design margins with integrated power/signal net electromigration/IR Drop analysis
  • Improving AMS design robustness with analog circuit ERC
  • Best practices in mixed-signal verification with advanced digital verification methodology with CustomSim and VCS
  • How to verify power and signal integrity for multi-gigabit circuits with HSPICE
  • Accelerating pre-layout design centering & optimization
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  • Custom layout productivity gain from using Custom Compiler’s visually assisted automation (Symbolic Editor, Interactive Routing, Template-based design)
  • Mixed custom/digital implementation productivity gain from using Custom Compiler co-design with IC Compiler II or Fusion Compiler
  • Faster analog design closure from using Custom Compiler early-electrical analysis with StarRC (in-design RC and EM, partial-layout simulation flow)
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  • Trading off performance vs cost for design or verification in a cloud environment
  • Security concerns and best practices in migrating from on-prem to cloud for design and verification
  • Allocation and usage of cloud resources for library characterization, simulation, timing analysis and parasitic extraction
  • Maximizing available resources with ICV elastic CPU usage
  • Impacts on design size partition for physical implementation in a cloud environment
  • Leveraging tool runtime scalability in the cloud; what worked best
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  • Raising the bar on achieved PPA with Fusion Compiler convergent flow
  • Optimal design flow for digital implementation of advanced node designs
  • Accelerating time-to-results for large designs with Design Compiler Graphical and IC Compiler II
  • Shift-left convergence with RTL Architect by improving constraints and RTL restructuring
  • How to achieve best Performance, Power and Area for Arm CPUs
  • Using parallel processing to accelerate physical and full chip timing signoff
  • Accelerating full chip TAT for large designs using IC Validator physical signoff
  • Optimization techniques for low-power IoT designs
  • Early time-based peak power analysis with PrimePower with RTL-based vectors
  • Using physical-aware ECO capabilities to improve PPA and accelerate timing closure
  • Design implementation on the Cloud
  • Extending the envelope of Moore’s law with 3D / 2.5D IC design; lessons learned
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  • Getting to fast physical verification at 7nm and below
  • Leveraging ICV multi-CPU scalability for fast time-to-results
  • Maximizing available resources with ICV elastic CPU usage
  • Dirty design handling during SoC integration to minimize runtime and maximize productivity
  • Shift-left physical verification analysis and repair utilizing Fusion technology in IC Compiler II and Fusion Compiler
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  • Success with early RTL analysis, physically-aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
  • Use of software analytics for accelerating product introduction as well improving yield, test times and quality during high volume production
  • Highlighted SoC application areas include AI, automotive, mobile and processors
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  • Interface IP such as 112G Ethernet, Die-to-Die, PCIe 5.0, DDR5/LPDDR5, etc.
  • Embedded ARC processors & embedded vision processors
  • OTP NVM, embedded memories & logic libraries in advanced FinFET processes
  • Integration of IP into high-performance computing, automotive, AI/ML or IoT designs
  • Integration of PVT sensor IP monitors and subsystems for enhanced device screening, power and performance optimization, and enhanced resiliency
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  • Accelerating software bring-up with emulation and prototyping
  • Software-driven power analysis for GPUs and AI
  • Prototyping with real-world interfaces
  • Large complexity prototyping
  • Pre-Silicon networking system validation
  • SoC performance validation using emulation
  • Trust and hardware security verification
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  • Faster and better convergence using formal methods
  • Verification coverage planning and closure
  • Best practices for static verification (Lint/CDC/RDC/SDC/LP) signoff
  • Accelerating verification and debug for advanced protocols
  • Innovations in verification methodology for optimized performance
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Copyright Statement

Please carefully read the following notice before submitting your written materials to the SNUG program.

By submitting materials to the SNUG program, you and your employer are giving Synopsys the following rights: (1) to reproduce, publish and distribute the submitted materials on the SNUG web site and Virtual platform for access by Synopsys employees, contractors, and licensees.

It is your responsibility to confirm your employer agrees to the use described above. You and your employer reserve the right to modify the submitted materials at any time. Synopsys shall reproduce any copyright or other legal notices you include in your submitted materials. Synopsys will not use your submitted materials for product marketing purposes without first obtaining your express written consent.

In addition to the copyright statement above all presenters will be required to submit a signed video release to Synopsys along with their final presentation slides and MP4 recording.

If you have any questions about this copyright statement, please contact the SNUG team before submitting your proposal.

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Contact Information

If you have any questions, please contact the SNUG team

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