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Reliability is becoming a mandatory design concern across many chip design cycles, particularly those expected to last for more than a couple of years. Some chipmakers see this as an opportunity to develop a more reliable device. However, finding the best method to accomplish this can be challenging.
Specifically, the chip design flow has begun to anticipate and respond to reliability issues that stem from circuit aging. For this reason, power and thermal issues have taken center stage in development, beginning at the architectural level. In this article, we’ll take a closer look at design for reliability and what engineers are doing to ensure chip reliability.
Design for Reliability (DfR) is a process meant to ensure a given product, system, device, or chip performs its intended function within the predefined usage environments over the expected lifetime. DfR should occur at the design stage before prototyping.
DfR refers to the entire set of tools, analyses, and considerations that supports products from early development to the end of the product life cycle. It is a streamlined, systematic, engineering program where reliability engineering is considered throughout the development cycle.
DfR relies on a wide array of engineering practices and tools, focusing on the order of development that an organization should follow to create reliable products. An effective design for reliability approach can be summarized in three statements:
Ultimately, a design for reliability framework is essential for reducing warranty costs and increasing customer satisfaction. Having your device fail in the customer's hands can be a very costly occurrence.
As devices continue to increase in complexity, processes that implement reliability measurements and best practices throughout the design process become even more necessary. Without a well-defined process, reliability procedures may not be deployed effectively, wasting resources and time.
For this reason, engineers and managers must work together to create a structured process to implement DfR. Additional reasons that stress DfR’s importance include better product differentiation and reliability assurance. As electronics age, fewer methods are available to set a product apart from the competition. Likewise, as new requirements, advanced circuitry, and new materials are incorporated into devices, it becomes more important than ever to ensure reliability.
Good DfR practices require cohesive integration throughout the product design cycle. In the long run, it is less expensive to design for reliability than to test for reliability. In the initial product stages during concept development—this is when DfR is most effective.
Circuit aging is a major focus of reliability design in the silicon industry. In the past, DfR applied to automotive or extreme stress environments; nowadays, it has become a mainstream consideration. As the demand for reliability increases, some foundries are beginning to provide aging models for customers.
Temperature is one of the largest factors impacting chip lifetime. Operating chips at increased temperatures will affect the chip’s lifetime and aging speed. Another major factor designers may control is current consumption. With a higher current draw, the chip’s lifetime can be reduced due to electromigration and other undesirable effects. As chips operate at lower voltages but stay in the same power envelope, higher current consumption results. This outcome is exacerbated by higher operating temperatures, creating an even more challenging reliability problem.
When the device is placed inside a package, mechanical stress, warpage, and other thermal mismatch factors may compound to reduce device reliability. Digital and analog chips are affected differently, and spots on a circuit with frequent voltage fluctuations are more sensitive to aging.
Reliability also depends on device size and channel length. Shorter channel lengths result in stronger electric fields and other undesirable effects. As the length and width of transistors are scaled down, the gate oxide may not scale at the same pace, adding additional device stress. Furthermore, voltage cannot be scaled at the same pace, as it will result in a lack of headroom above the device’s threshold voltage. All of these factors result in increased stress that designers must consider.
Chip designers are beginning to incorporate aging models into their designs in an attempt to increase reliability. However, uncertainty persists. Processing variations, self-heating effects, Monte Carlo, and other effects must all be taken into account to analyze a circuit’s longevity. Only time will tell whether these models will be accurate.
Designers use various analysis tools, simulation models, and reliability data to determine specific operating conditions for their devices. Designers also measure chip conditions in real-time to see how the chips degrade. In doing so, they can take steps to mitigate and manage these aging processes. By focusing on creating good aging models and implementing an aging simulation flow, designers are able to leave less on the table.
Additionally, designers can monitor the conditions—or device asserts—within which a device operates. In examining the electric field and spots with high voltages, designers can locate sensitive areas that could cause potential problems down the line. Experienced designers may also know which blocks are more sensitive to specific aging phenomena and account for them in the design process.
Synopsys is the industry’s largest provider of electronic design automation (EDA) technology used in the design and verification of semiconductor devices, or chips. With Synopsys Cloud, we’re taking EDA to new heights, combining the availability of advanced compute and storage infrastructure with unlimited access to EDA software licenses on-demand so you can focus on what you do best – designing chips, faster. Delivering cloud-native EDA tools and pre-optimized hardware platforms, an extremely flexible business model, and a modern customer experience, Synopsys has reimagined the future of chip design on the cloud, without disrupting proven workflows.
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