Industry's First Verification IP for PCIe 7.0

Aditi Sharma

Jun 13, 2024 / 2 min read


In our recent blog, Synopsys Accelerates Trillion Parameter HPC & AI Supercomputing Chip Designs with Industry's First PCIe 7.0 IP Solution, Synopsys announced the first comprehensive PCIe Express® Gen 7 (PCIe 7.0) IP Verification IP (VIP) solution to support the speed and low latency required for Artificial Intelligence (AI) applications in high performance computing designs.

PCI Express Evolution

Since its launch in 2003, PCI Express has undergone continuous advancements in technology, specification, and transfer speed, demonstrating its success as a standardization initiative and data transfer protocol. PCIe 5.0 powered cloud computing resources with 32G transfer speeds and CXL coherency, while PCIe 6.0 doubled performance to 64G transfer rates using Flow Control Units (FLITS) and PAM4 modulation for effective, low latency communication and coherency. PCIe 7.0's load-store capabilities and up to 512 GB/s of bandwidth for secure data transfers make it possible to connect multiple accelerators and process large, complex AI and machine learning models efficiently. 

I/O Bandwidth Doubles Every 3 Years. Image Credit PCI-SIG

What’s new in the PCIe 7.0 specification?

PCIe 7.0 specification includes the following features:

  • 128 GT/s data rate and upto 512 GB/s bidirectionally via x16 link
  • PAM4 signaling
  • 1b/1b flit mode encoding
  • Forward Error Correction (FEC)
  • Greater power and cost efficiency
  • Data security with IDE protocol
  • Backwards compatibility with older versions of the specification
  • Sleeping state for flexibility and low power
PCIe generational performance

Synopsys PCIe 7.0 Verification IP (VIP) Features

Synopsys Verification IP (VIP) for PCIe provides verification of design implementations based on all PCIe specifications (PCIe 1.0 to 7.0) which can be used in SoCs and System Level Desings to accelerate verification closure.

With support for PCIe 7.0, the Synopsys PCIe Verification IP solution addresses design verification complexities through following features:

  • Support for data rates up to 128.0 GT/s per lane while maintaining backward compatibility in Root Complex (RC) and Endpoint (EP) devices for seamless transition from Gen6 to Gen7.
  • Native System/Verilog UVM architecture, which facilitates easy integration into simulation environments and speeds up the development of test benches.
  • Integrated verification plan, test suites, and functional coverage, to expedite the verification process and gain a competitive edge.
  • IDE-based data integrity and security protections, to prevent data and system breaches.
  • Rich configurability options and built-in protocol checks, to stay competitive in a market where protocol developments are already being adopted.


Synopsys is partnering with early customers and collaborators to enhance the standard architecture for their next-generation designs, incorporating new features now available with the latest specifications.

Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer.

Running system-level payload on SoCs requires a faster hardware-based pre-silicon solution. Synopsys transactors, memory models, hybrid and virtual solutions based on Synopsys IP enable various verification and validation use-cases on the industry’s fastest verification hardware, Synopsys ZeBu® emulation and Synopsys HAPS® prototyping systems. 

More information on Synopsys PCIe® VIP and Test Suites is available at

Continue Reading