Faster, Higher Capacity Emulation and Prototyping for AI Workloads

Samskrut Konduru

Mar 20, 2024 / 4 min read

From large, monolithic SoCs for AI workloads to complex multi-die systems, today’s chip designs are creating greater challenges for software and hardware verification. As the number of gates extend into the billions, the capacity needed to enable engineers to get to the root cause of software and chip flaws and failures has ballooned. And with ever-present time-to-market pressures, speed joins capacity as two key demands on verification systems.  

Answering the call for greater capacity and speed is the latest version in the Synopsys ZeBu® EP family of unified emulation and prototyping systems. Synopsys ZeBu EP2 provides the fastest emulation platform for AI workloads, making it ideal for software/hardware validation and power/performance analysis. Offering prototyping capabilities as well, ZeBu EP2 shares a common hardware platform with the Synopsys HAPS-100 12 FPGA-based prototyping system. Together, these offerings expand the industry’s broadest hardware-assisted verification (HAV) portfolio, helping you reduce design risks and ensure that your complex designs will perform as intended.

Read on to learn more about key use cases for ZeBu EP2 and HAPS-100 12 FPGA and how they can help you achieve silicon success with flexibility, scalability, and efficiency.

ai chip design emulation and prototyping

Key Use Cases for ZeBu EP2

As our electronics become increasingly intelligent, software is playing a larger role in the underlying designs. For these software-defined systems, it’s vital for the hardware and the software to be co-designed holistically. The starting point tends to be software workloads that need to be supported, after which the silicon can be built to meet both the software and the system’s needs.

By unifying emulation and prototyping on one HAV platform, ZeBu EP2 frees design teams from the constraints of having to choose one or the other HAV product. Traditionally, hardware verification teams would rely on emulators for fast SoC design verification, while software development teams would look to prototyping solutions for the additional boost in performance. The ZeBu EP family allows both teams to let their projects dictate how and when to shift capacity between emulation and prototyping, instead of having to estimate resources beforehand.

"Investing in a scalable, single hardware platform for emulation and prototyping provides a significant economic advantage,” said Vincent Cheng, engineering vice president at Phison." As our storage designs typically involve many different products variants for many different applications, we are looking forward to continuing to benefit from the ZeBu EP product family for greater flexibility in our hardware resources as well as the scalable capacity it provides as we switch between emulation and prototyping.”

While our newest ZeBu EP2 platform supports all verification use cases, a key one is software/hardware validation. Consider the case of AI SoCs: given that these architectures have a specialized compiler, designers must ensure that the software stack will work. And anytime there’s a change in the hardware, the compiler that maps any AI model to that hardware must also be changed. In addition, it’s also critical to validate that key interfaces will work in the external world. This is where software/hardware validation through emulators come in. By mimicking the behavior of the hardware, emulators provide a realistic test environment to evaluate how the software will interact with the hardware without requiring a physical device. By testing their software code early, developers can get a head start on bug detection and resolution. The addition of speed adapters enables the emulator to run at near real-time speeds for a better understanding of a system’s actual behavior in the final target system environment.

The other key use case where our emulator really shines is power/performance analysis. Going back to our AI SoC example, by optimizing the chip’s specialized compiler through emulation, engineers can thereby influence the power and performance of their device. Since emulation enables testing of the system under realistic operating conditions, engineers can gain an understanding of how different workloads and usage scenarios can impact power and performance and optimize their design accordingly. As with the previous use case, they can also get a jump on detecting and resolving any issues.

Key Use Cases for HAPS-100 12 FPGA

The HAPS-100 12 FPGA prototyping platform is the HAPS family’s highest capacity and density system, with a mix of fixed and flexible interconnects and a rack-friendly design. The fast-performing platform is particularly useful for prototyping big designs that require many FPGAs, such as multi-die systems and large SoCs. Like its HAPS-100 4 FPGA predecessor, the HAPS-100 12 FPGA platform also enables high debug productivity and supports multi-design, multi-user deployments for distributed verification teams.

For large designs, it becomes costly to build a large prototype system and, as the model gets larger, model build times become unpredictable and require a lot of compute resources. A modular HAV flow can provide a more efficient and effective alternative. Using such a flow with the HAPS-100-12 FPGA platform, verification engineers can build and optimize their prototype model for a single die and then configure that model for single-die or multi-die hardware without having to do multiple projects.

“Validating our multi-die design against real-world interfaces and scenarios with the high-performance HAPS prototyping platform enables us to optimize our design early on, with faster build times and more predictable results,” said Lam Ngo, principal engineer at Microsoft. “Having a common hardware platform for different prototype models means we can shift the hardware to use on large or small models in real time, with reduced compute and storage resources and the ability to easily and quickly scale as our needs require.”

A Less Daunting Path for AI Chip Design Verification

In our era of pervasive intelligence, chip designs are growing more complex as engineers uncover clever ways to meet bandwidth and performance demands while extracting more out of Moore’s law. Against this backdrop, HAV solutions such as the ZeBu EP2 and HAPS-100 12 FPGA platforms provide the speed, capacity, and flexibility needed, whether the design is a large AI SoC or a multi-die system. With choices like these, engineering teams can let their project demands, and not the hardware, dictate how they’ll manage their verification resources. 

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