Highlights
- Native SystemVerilog/UVM
- Runs natively on major simulators
- Built-in protocol checks
- Built-in verification plan and coverage
- Source code test suite
- Error injection
Synopsys® VC Verification IP for MHL provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MHL devices operating with TMDS and CBUS links.