VC Verification IP for MHL

Synopsys® VC Verification IP for MHL provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of MHL devices operating with TMDS and CBUS links.

Verification IP for MHL


  • Native SystemVerilog/UVM
  • Runs natively on major simulators
  • Built-in protocol checks
  • Built-in verification plan and coverage
  • Source code test suite
  • Error injection

Key Features

  • Supports MHL 3.2 specification
  • TMDS and CBUS link interface
  • MHL Audio and Video formats
  • TMDS packetization
  • All supported quantization and colorimetry
  • 3D Video, High-End Video
  • Audio (ACR, ASP, CMP)
  • Audio/Video info frames
  • MSC/DDC/eMSC Commands
  • EDID access