Why Multi-Die Systems, Why Now?
At the very core of the movement to multi-die systems is the insatiable thirst for faster, better, and smarter. The drive to cram more and more functionality, and with that more user experiences into products and services. For many years, Moore’s law-driven scalability met these needs.
However, device scaling is slowing and the benefits of moving to newer nodes are diminishing while costs are increasing — trends that will continue as we get into the Angstrom era. Yet the drive for compute, further fueled by ubiquitous AI is creating immense demand for highly complex and increasingly heterogeneous systems to address functionality and user experience needs.
The situation presents a perfect storm. If the chips can’t scale as an answer to the growing compute-density and functionality demands, and the market demands these complex systems — we need a different answer. And that answer is multi-die systems.
How Real is the Multi-Die System Trend?
Simply put, it’s very real and it’s happening now. Synopsys works with many advanced system OEMs to develop next-generation semiconductor designs. We’ve already worked with quite a few customers to integrate multiple dies into a single package.
The economic benefits of a multi-die system approach include re-use of proven chip technology to create multiple SKUs in a product family. Large designs that approach the reticle limit, or maximum die size suffer from low yield, resulting in high silicon cost. Decomposing a large design into smaller chips results in much better yield and associated silicon cost.
From a physics perspective, ubiquitous sensing, analog processing and many types of communication don’t benefit from advanced scaling. A system composed of optimized blocks, built with the optimal process technology presents a better alternative.
In November 2022, Synopsys held its yearly Global User Survey. 6,025 people responded to the survey which touched on many design and technology trends. The companies responding had a worldwide footprint and the respondents came from a broad range of job categories and disciplines.
A question regarding multi-die system usage revealed a strong adoption trend. The question asked respondents about plans to use 3D-IC technology, including thru-silicon vias (TSVs). Over 50% of respondents were either using or planning to use this technology.
How Does the Multi-Die System Approach Impact the Design Flow?
All of the challenges faced in monolithic 2D chip design still must be addressed for multi-die systems. But the scale is much larger. The potential interactions between parts of the system are also greater. There are complex thermal and power management challenges within the package, architectural partitioning, and partitioning for the massive software stacks that interact with the hardware for example.
The multi-die system journey begins with partitioning between hardware and software. Each of the dies in a muti-die system could have its own software stack. And verifying this software in the context of the hardware it’s going to run on is important. Synopsys has very successful solutions available for monolithic 2D chip design, and we’ve expanded those to enable the more complex verification problem presented by multi-die systems.
We have solutions like Platform Architect for early functional architectural exploration, and Virtualizer with the largest System C IP library to enable efficient virtual prototype assembly. And the HAPS prototype system, which delivers high-speed I/O verification as well as mixed voltage support. We offer the ZeBu and ZeBu Hybrid emulation platforms with very high scalability, which can handle the many use cases encountered in a complex multi-die system.
There are also unique power and thermal challenges. These become firstorder effects and must be analyzed very early. To address this need we’ve partnered with Ansys to bring their best-in-class solutions for signal, power and thermal integrity into the design flow, alongside Synopsys’ golden signoff solutions, PrimeTime and StarRC. This is all delivered with the 3DIC Compiler solution that provides a unified platform to integrate tens to hundreds of heterogeneous dies in an optimized system for performance, power, and thermal effects.
Beyond design tools and methodology, IP is a critical enabler for multi-die systems. IP that fuels chiplet design and IP that facilitates communication between the dies in a muti-die system. Synopsys has the broadest IP portfolio in the industry with leading offerings across many titles, including a comprehensive die-to-die IP solution.
As we approach the end of the design process, system testability and reliability become important. The challenge here is not just taking all known good die and putting them together in a single package, it’s about ensuring the health of the system all the way through its lifecycle, including in-field operation.
Synopsys has many solutions here like the extended TestMAX, as well as a portfolio to support silicon lifecycle management with tools, in-chip monitor IP and analytics to help the system through its journey in the field with reliability and security.
So, the entire multi-die system design journey is covered from early architecture, to physical design and verification to deployment in the field.
Where Do Chiplets Fit?
The term chiplet has many meanings. In general, a chiplet represents a bare-die version of a chip design that can be integrated with other components using high-density integration methods to form a complete system in a package. Chiplets can be used to implement small functions such as sensors all the way to large processor arrays that are as big as large monolithic designs.
For example, a popular use case is I/O disaggregation where compute engines are in one die and I/O are in a separate die. Enabling effective use of chiplets requires focus in two areas.
One is standardization of use cases for chiplets, such as the work being done by UCIe. This work addresses aspects such as electrical parameters, compliance with other standards, interoperability, and form factor.
The other is the supporting methodology, such as top-level partitioning, software development, testability, and silicon lifecycle management.
Both areas are important for the development of an industry-level chiplet ecosystem.
At Synopsys, we have the IP, the IP subsystems, the tools, methodologies and flows to help enable a chiplet ecosystem. We are also working with organizations such as the ODSA, part of OCP and the UCIe Consortium, along with all their partners and members to address the technical and the business challenges so multi-die systems can have broader adoption across the market.
Synopsys is also introducing AI into the multi-die system design flow to deliver step-function improvements in design efficiency and quality of results.