Discover the power of Synopsys Proteus™ full-chip mask synthesis smart manufacturing solutions enabling technologies down to 3nm and below. With the Synopsys Proteus family you can achieve exceptional precision, efficiency and speed in proximity correction, model building for correction, and analyzing proximity effects on corrected and uncorrected IC layout patterns, revolutionizing your chip fabrication process.  The Synopsys Proteus full-chip mask synthesis family are the products of choice for leading edge IDMs and foundries and have been production proven for two decades with support for the latest EUV lithography processes.

Key Benefits

Largest Lithography Entitlement

Industries first and most deployed inverse lithography solution with native curvilinear design and mask support.


Fast Turn Around Time

AI driven solutions with advanced computation support for latest CPU and GPU technologies to reduce time to market.

Highly Predictive Models

Advanced compact 3D resist and mask models and industries only mask synthesis tools with rigorous physics-based model support through S-Litho.

Explore Proteus Solutions

Providing Model-Based Correction of Proximity Effects

Proteus Optical Proximity Correction (OPC) delivers the most accurate OPC results and fastest turnaround time for both dense and sparse designs with curve mask feature support for the highest quality on advanced dense designs. Proteus’ programmability and modularized applications provide optimal flexibility while ensuring protection of valuable customer IP.

Advanced Correction of Optical Proximity Effects

Proteus Inverse Lithography Technology (ILT) is the industry’s first and most widely production deployed inverse lithography solution, providing the largest process windows, higher yield, and faster time to market while delaying the need for costly new hardware and multipatterning technologies.  Native support for curve design and mask features, flexible cost functions, automated pitch relaxation on routing layers, and co-optimization of assist and main features consistently deliver the largest process entitlement for latest advanced high-density designs.  Full chip application support is available with efficient handling of periodic and hierarchical structures, application of AI, and support for the latest advances in compute hardware.

Comprehensive Full Chip Hotspot Detection and Mask Validation

Proteus Lithography Rule Check (LRC) provides post OPC verification tools for full chip mask validation with industry-leading accuracy.  Proteus LRC delivers fast comprehensive hotspot, two-layer spacing and overlay, stitching, process variability, EPE, and CD control checking capabilities through the process window to quickly identify hotspots to support more robust design practices and hotspot resolution prior to committing a design to mask manufacture.  

Rule-Based Assist Feature Placement for Larger Common Process Windows

Proteus RBAF2D provides geometric driven AF placement for fast consistent AF insertion with advanced 2D AF placement capabilities for increased depth of focus (DOF).  An ILT-based model assisted rule table (MART) utility automates the extraction of optimal rules for faster AF rule creation using simulation-based rule extraction requiring only a single mask to establish rules.

Rule-Based Technologies and Layer Operations to Simplify GDS-to-Mask Flow

User friendly table driven OPC and complete set of primitive polygon manipulation commands to support biasing and localized cleanup / data preparation operations.  

Comprehensive pattern matching engine for fast and consistent correction flows and quick resolution of yield-killing design sensitivities.

Complete Fracture Within Minutes After Correction

CATS industry leading fracture capabilities are integrated into the Proteus mask synthesis flow for parallel processing of correction and fracture with direct handoff to the mask writer for efficient data handling, and reduced I/O.  Providing the fastest path to mask write.

Deliver Production-ready Solutions

Proteus SMO enables users to perform a source mask co-optimization (SMO) task within a very flexible and customizable environment.  Within the application flow, the mask treatment is realized by using the Proteus ILT or Proteus OPC engine with customer specific, production proven recipes.  This ensures best lithographic performance when transferring the SMO solution to a full-chip correction flow.

Productivity Environment for Mask Synthesis Applications

Proteus WorkBench (PWB) is a powerful cockpit tool for the development and optimization of Proteus-based mask synthesis solutions. It is based on a powerful hierarchical GDSII/OASIS layout visualization and editing engine, providing a comprehensive environment for lithography simulation, compact model building, optical proximity correction (OPC) recipe tuning, litho rule checks, and mask synthesis flow development.

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