High-Level Synthesis from C/C++ to RTL
Synphony C Compiler reduces development time and cost by shifting the focus of hardware implementation from designing at the RTL level to designing at the algorithmic level. Designers describe hardware in algorithmic C/C++, using Synphony C Compiler to fine-tune the architecture for tradeoffs in performance, power, and area, and generate highly optimized RTL implementations for ASIC or FPGA. The tool infers the necessary interfaces and memory structures to implement an optimized architecture, eliminating the need to code explicit parallelism and control logic. It is capable of handling multimillion gate hierarchical designs with efficient hardware sharing across layers of hierarchy.