Synphony C Compiler

High-Level Synthesis from C/C++ to RTL

Synphony C Compiler reduces development time and cost by shifting the focus of hardware implementation from designing at the RTL level to designing at the algorithmic level. Designers describe hardware in algorithmic C/C++, using Synphony C Compiler to fine-tune the architecture for tradeoffs in performance, power, and area, and generate highly optimized RTL implementations for ASIC or FPGA. The tool infers the necessary interfaces and memory structures to implement an optimized architecture, eliminating the need to code explicit parallelism and control logic. It is capable of handling multimillion gate hierarchical designs with efficient hardware sharing across layers of hierarchy.

Benefits

  • 5-10X productivity increase over manual RTL coding
  • Superior quality-of-results (QoR) for area and timing using Design Compiler® for RTL synthesis and Synplify for FPGA synthesis
  • Faster turnaround time implementing large, multi-million gate designs
  • Seamless end-to-end verification from the original C/C++ model to RTL validation and verification environments

 

High-level synthesis to accelerate design of image processing IP

Synphony C Compiler enables high-level synthesis, simulation and debug from C/C++.