The Choice of Transistor Architecture for the 5-nm Node and Beyond

The Choice of Transistor Architecture for the 5-nm Node and Beyond

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Increasing the fin-height in FinFET devices helps designers meet aggressive area shrink goals – in concert with fin depopulation – but comes with added complications in increased parasitics and greater manufacturing challenges. Synopsys has long been working across the industry to research, enable and thus chart a path for what transistor architectures will look like beyond the FinFET. In this video, Synopsys R&D will discuss the most likely options for transistor architectures as we move beyond the 5-nm node and how this is demanding a broader solution of “variability-driven engineering”.