Q: Welcome Vineet. Synopsys recently unveiled RTL Architect. Can you tell us more about the motivation for this new product and its significance?
Certainly. We have seen over the last few years that increasing complexities of advanced process nodes has made it much harder for design teams to achieve their PPA goals. In addition, the emergence of new market verticals such as AI and automotive require customers to do early and rapid architecture exploration to meet the PPA targets. This challenge of deriving best PPA has moved upstream in the RTL-to-GDSII flow and has put a lot of pressure on RTL designers to dramatically improve RTL quality prior to any implementation feedback. However, the process today is not efficient since it lacks a platform for RTL developers to accurately measure the PPA impact of their RTL modifications.
Synopsys’ RTL Architect has been designed to address this RTL design closure challenge. It is the industry’s first physically aware RTL analysis, optimization and signoff system, built from the ground up for superior RTL handoff. It enables RTL designers to quickly achieve superior RTL and reduces the SoC implementation cycle in half.