1:1 Mo Movahed-Ezazi

Q: Hi, Mo. Thanks for taking the time today. Please share your vision on extraction products and how the market is driving the direction for extraction products to serve the customer base.

Mo:

The semiconductor design ecosystem is rapidly evolving with the introduction of 3D devices at advanced nodes, 3DIC technology, and integration of various components on the same die. Co-design at the chip level, and chip-package co-design flows, are gaining prominence. These market drivers dictate the direction for parasitic extraction tools.

StarRC and QuickCap R&D continue to invest and innovate in several important areas. This includes scalable runtime and capacity of our core extraction and field solver technologies, productivity and ease-of-use, and advanced capabilities to support evolving design challenges in growing markets including custom design and 3DIC. We are innovating to support gate-all-around (GAA), vertical FET (VFET), complimentary FET (CFET), and other upcoming 3D device technologies. Our collaboration with foundries and leading design companies is stronger than ever giving us a dominant position as the golden signoff extraction tool. 

Our integration with custom and digital platforms has been enhanced in 2020 to provide sign-off accurate extraction and seamless user experience for all of our newly introduced features.. StarRC enjoys a dominant position in the digital design market and our goal is to achieve similar status for the custom design market.

Q: How do you see the custom design market evolving and StarRC’s position to address these changes?

Mo:

Custom design refers to analog mixed-signal (AMS), co-design flows, and represents around 30% of the extraction market. Leading markets like AI, 5G, automotive, and HPC are driving the demand for SoCs which have all types of blocks on the same IC. These in return are driving a broader adoption of AMS, co-design flows within semiconductor design companies. StarRC has a strong position in the digital and analog extraction market and since our December 2019 release, we have started focusing on the custom market. Our StarRC Ultra+ Custom product is targeted for custom design flows with features that include inductance extraction, field solver based resistance extraction, standalone netlist reduction, netlist optimization for simulation speed-up, a transistor-level parasitic debug environment,  and integration with Custom Compiler and third-party custom design tools. 

Q: What challenges do you see for advanced node designs and the role StarRC plays for building confidence in the design flow?

Mo:

StarRC leads in advanced process modeling, and supports accurate parasitic extraction for 3D devices such as GAA, FinFET, accounting for multi-patterning, and color aware variations. We closely collaborate with leading foundries to design the modeling methods that meet the most stringent accuracy criteria compared with silicon. StarRC is fully certified by leading foundries for advanced process nodes down to 3nm and is widely used by tier one design companies for both gate and custom level extraction. As our R&D team works directly with foundry technology teams and routinely starts working on the next node well ahead of time, our solution matures and often gets ready earlier than our competition. 

In addition to advanced nodes, StarRC provides equally strong support and foundry certification for established nodes. We have many customers that use established nodes, while foundries continue to refine the process.

Q: 3DIC technology is an exciting area and the ecosystem is growing, what is StarRC doing to enable 3DIC designs?

Mo:

We continue investing in developing a comprehensive extraction solution in support of multiple 3DIC technologies like; CoWoS (Chip on Wafer on Substrate), WOW (Wafer on Wafer), EMIB (Embedded Multi-die Interconnect Bridge), SOIC (System on Integrated Chips), InFO-LSI (Integrated Fan Out – Local Si Interconnect), and InFO-WLP (Integrated Fan Out – Wafer Level Packaging). As an industry leader in extraction, StarRC enables designers to extract through-silicon-vias (TSV) with RLC custom models, TSV-to-TSV coupling extraction, and grounded & floating substrate.With our latest support for inductance and all-angle extraction, we have increased our R&D effort to extend our 3DIC solution to support high-speed interconnect RLC extraction with s-parameter for higher accuracy and frequency between high-bandwidth memory (HBM) and logic cores by early 2021. Many of our customers are excited and we are closely working with foundries to enable our customers on their ongoing projects.

Q: As I understand it, QuickCap is also in your portfolio. Can you elaborate on the recent improvements of the tool and applications it is targeted for?

Mo:

QuickCap is indeed in our portfolio and is an industry golden 3D field solver. Construction of the tech file (QTF) used by QuickCap makes it well suited for extraction of 3D devices and the tool comes with a 3D visualizer. Recently we have given a 40x performance boost to the tool with patented distributed field solver technology. Faster speed and higher capacity are opening up more applications, and we are developing flow support for LEF/DEF input and an IC Validator flow. The leading foundries in the world use QuickCap as their plan-of-record tool. The target applications of QuickCap include - process exploration, PDK development, standard cell characterization, high accuracy analog cells, golden extraction reference, and many others.

Q: To wrap up, can you comment on the availability of this product?

Mo:

With highly competent and dedicated R&D & PAE teams and their unwavering commitment to innovation and customer support, I am confident in our ability to continue delivering the best and most differentiated industry golden extraction and 3D field solver to our customers and foundry partners. Synopsys StarRC Ultra+ Custom and StarRC Ultra+ Digital were released in early 2020 and StarRC AG3 (3nm solution) was released in June 2020. We continue to invest heavily in these products and plan to roll out new, highly differentiated technologies in the first half of 2021.