Cloud native EDA tools & pre-optimized hardware platforms
Arm and Synopsys have been collaborating for more than 25 years to enable design solutions for our mutual customers across the entire design flow. This includes optimized implementation, design & verification, system validation and software design, and HW/SW integration, and lately even software security/quality.
A significant early collaboration was our work in 1997 to create Arm’s first synthesizable cores, the ARM7-S and ARM9-S, and immediately after that, implementation flows to reliably implement those cores with excellent performance, power, and area (PPA). Since that time, Synopsys has collaborated with Arm to build QuickStart Implementation Kits (QIKs) for leading-edge Arm processors, and we make these available for customer download through SolvNet.
As Synopsys’ executive sponsor for Arm, I’m fortunate to oversee these collaborative activities. I also have a dedicated customer engagement team focused on Arm cores, with many years of Arm processor implementation expertise. This team works closely with Arm designers during processor development to create the QIKs and support Arm core early adopters.
QuickStart Implementation Kits are a very good example of collaborative joint work between Arm and Synopsys in support of mutual customers. The QIKs, available for leading-edge Arm processors at beta release, serve as an optimized starting point for implementation using Synopsys tools. They are basically a complete and comprehensive “cookbook”. Each QIK includes scripts, baseline floorplan, design constraints, and documentation to enable high-performance, low-power implementation using the Synopsys Fusion Design Platform for a specific Arm processor and its POP™ IP.
We offer the collaboratively-developed QIKs as an optimal starting point for implementation. Our Arm core center-of-excellence offers Arm Core Hardening services, from QuickStart through full turnkey core implementation. In addition, Synopsys’ Application Engineers worldwide also have deep Arm core implementation knowledge to assist customers with their designs.
Concurrent with Arm’s launch of their latest mobile and infrastructure platforms, we announced multiple customer tapeout successes that utilized Synopsys’ Fusion Design Platform and Verification Continuum Platform, as well as DesignWare IP. In addition, we announced the availability of 7-nanometer QIKs for the Cortex-A76 and Cortex-A55 premium mobile CPUs, as well as the next-generation Neoverse® “Ares” server-class CPU. In both cases, the Arm-Synopsys collaboration enabled early adopters of Arm processors to successfully tape out before these cores were generally available in the market.
Also, throughout the year, Arm and Synopsys presented collaboration results, including best practices for hardening Arm processors, at many well-attended sessions at Arm TechCon, worldwide Arm Tech Symposia, SNUGs, Arm-Synopsys workshops, and the Design Automation Conference.
At Arm TechCon in October, HiSilicon presented their experience using Synopsys tools to achieve “optimum MHz/mW” on their Kirin 980 7-nm SoC. This mobile AI computing chipset includes 8 CPUs (two dual-core Cortex-A76 clusters and a quad-core Cortex-A55 cluster). We have many such success examples; to learn more I encourage you to go to: www.synopsys.com/Arm for customer videos and presentations.
We developed the Fusion Design Platform to help our customers realize the full potential of their leading-edge designs, and that includes Arm core hardening. The Fusion Design Platform redefines conventional EDA tool boundaries across synthesis, place-and-route, and signoff, sharing engines across the industry’s premier digital design tools and using a unique Fusion data model for both logical and physical representation.
Designers who are hardening Arm cores are taking advantage of the Fusion Design Platform to improve PPA and productivity, and to accelerate the delivery of their next-generation Arm processors. In our Arm-Synopsys 2018 workshops, ANSYS presented the benefits of using RedHawk Analysis Fusion within IC Compiler II on Arm CPUs, significantly reducing IR drop and delivering 5x productivity. In addition, we’re seeing excellent results with Fusion Compiler on current and next-generation Arm processors.