Cloud native EDA tools & pre-optimized hardware platforms
When designers start working on advanced-node designs at 7nm, 5nm, and below, they realize that physical verification complexity drastically increases, but their design timeline doesn’t. So, we looked at different ways to address the complexity problem and also reduce the overall physical verification cycle to reach final signoff.
The new technologies and features within IC Validator NXT deliver unparalleled productivity gains and enables designers to cut their physical signoff time by 2X.
IC Validator is a comprehensive and highly-scalable physical verification tool suite that includes DRC, LVS, PERC, metal fill, and DFM enhancement capabilities. It is architected for high performance and scalability that maximizes hardware utilization using smart memory-aware load scheduling and balancing technologies. By using multi-threading and distributed processing over multiple machines, it provides scalability benefits that extend to thousands of CPUs.
Another thing to note is that IC Validator is a cloud-enabled solution, so customers can quickly and easily access the technology.
Of course! First, there is the massively parallel distributed processing architecture that enables designers to run on more than 2,000 CPUs to complete their full-chip physical signoff run in mere hours.
Secondly, we have this “elastic CPU management” technology that enables designers to add and remove CPUs on-the-fly as the job is progressing. This technology helps designers run IC Validator jobs very efficiently by optimizing the CPU resource usage based on the job needs. For example, if the job requires 1,000 CPUs and only 40 are available, the IC Validator job can be launched immediately with available CPUs. More CPUs can be added dynamically during the run as they become available. This enables designers to start the jobs early and, therefore, finish the job early. Users can also add more CPUs to the job during peak to reduce the runtime. In the final stages of the run, you can release underutilized CPUs and redeploy them to start another job.
Because IC Validator is now a cloud-ready physical signoff solution, its scalability, elasticity, and low memory requirement, combined with support from ecosystem partners, has enabled leading customers to successfully deploy IC Validator signoff on the cloud for their tapeouts.
We have introduced new Explorer DRC technology as part of IC Validator NXT that enables designers to complete first chip finishing 5X faster on 5X fewer CPUs. The DRC heatmap capability provides a high-level viewpoint of where the hotspots are during chip integration, so you can resolve fundamental issues before running signoff, resulting in an order-of-magnitude debugging speed-up.
Our new Live DRC technology joins a signoff-quality geometry engine, foundry signoff runsets, and supported layout tools to enable signoff-quality in-context viewport DRC checking. Custom layout designers can run DRC directly from the layout canvas to get immediate DRC feedback within seconds. This enables an interactive design-and-verify flow and enhances designer productivity.
IC Validator NXT brings the power of full signoff physical verification into the design phase with IC Compiler II, without imposing time-consuming stream-in and stream-out of layout data. Using IC Validator NXT physical verification in the Fusion Design Platform, DRC and manufacturing issues are caught much earlier in the design cycle, reducing or eliminating late-stage surprises close to tapeout. Timing-aware fill and automatic DRC repair capabilities in IC Compiler II and Fusion Compiler enable place-and-route engineers to quickly converge on block physical signoff.
The Live DRC technology I mentioned earlier works with Custom Compiler to run DRC in memory within a custom environment to enable an interactive design-and-verify flow.