Cloud native EDA tools & pre-optimized hardware platforms
Certainly. This milestone builds on our numerous successful collaborations with Samsung, and validates the readiness of GAA architecture, the next-generation transistor technology. A key benefit of GAA is the realization of enhanced gate control and reduced internal parasitics that together demand optimization technologies to extract the process’ combined power, performance, and area (PPA) potential.
My team has worked closely with Jacob’s team for several years to tightly couple PrimeTime timing and StarRC parasitic analysis with IC Compiler II to provide full-flow, total-power-driven optimization with signoff-correlated results, thus accelerating the path to targeted PPA for advanced designs. In this instance, enhancements in IC Compiler II that tightly couple technologies across the placement, legalization, and routing stages have been key to Samsung Foundry achieving its overall logic-area shrink goals for their new GAA process.
At Synopsys, we strongly believe in innovation through partnership and technology leadership. In that vein, Synopsys and imec recently announced successful completion of the first comprehensive parasitic variation modeling and delay sensitivity study of complementary FET (CFET). This was another milestone in our longstanding partnership with imec, as this new architecture can significantly reduce area vs. traditional FinFETs.
In 3-nm and 2-nm process technologies, the magnitude of variation increases significantly for middle-of-line parameters, as well as interconnect, due to high resistance of metal lines, vias, and surface scattering. Our collaboration with imec enables fast and accurate modeling of parasitic variation and sensitivity for a variety of device architectures, and accelerates bringing CFET to mainstream production.
The imec-Synopsys partnership facilitates the optimization of CFET devices for better power/performance trade-offs while accurately accounting for cell and interconnect variation. This prediction at early stages of process development allows foundries to create more robust and variation-tolerant transistors, standard cells, and methodologies for metal interconnect. Process engineers can now understand the sensitivity of circuit performance to variations in process parameters and improve modeling accuracy.
Our joint solution for the accelerated modeling of variation-aware CFET technology will benefit the entire semiconductor industry. Utilizing the flexibility of Synopsys’ tools, engineers can better target and significantly reduce the number of trials needed to optimize circuit performance in the presence of process variation and reduce circuit sensitivity. This significantly reduces the overall turnaround time for device and circuit optimization.
Working with partners like Arm, NVIDIA, Qualcomm, TSMC, et al., on the IEEE Liberty Technical Advisory Board (LTAB) and Interconnect Modeling Technical Advisory Board (IMTAB), we recently ratified new modeling constructs to address timing and parasitic extraction challenges at process nodes down to 2nm. This will allow our partners, as well as other customers, to bring the highest-quality 3-/2-nm designs to market in the shortest time possible.
Mobile device requirements for ultra-low power, as well as device architectures, mask, and patterning techniques at these nodes, result in artifacts that must be modeled by new extensions in the interconnect technology file (ITF). Extraction modeling in the ITF file now addresses gate resistance for new device architectures, as well as patterning extensions on interconnect and trench contact structures. In addition, the Liberty standard has been enhanced to provide better insight into the assumptions used for computation of dynamic power values in the library models.
Absolutely. We have a significant, focused effort on Design Technology Co-Optimization (DTCO) wherein we are driving a ‘shift-left’ philosophy with foundries and IDMs. A major challenge for foundries is to converge on the best architecture in a timely manner while vetting all the possible options. DTCO enables pathfinding of new process technologies, starting even before wafers become available.
Recently, we announced a DTCO collaboration with IBM for efficiently evaluating and down-selecting new transistor architectures, materials, and other process technology innovations using design metrics. The collaboration will extend the Synopsys DTCO tool flow to new transistor architectures and other technology options while enabling IBM to develop early process design kits (PDKs) for its partners to assess the power, performance, area, and cost (PPAC) benefits at IBM’s advanced nodes.
Synopsys has developed the only complete DTCO solution, from materials exploration to block-level physical implementation, thereby contributing to faster process development at reduced cost. Synopsys’ accurate materials, lithography, process, and device TCAD simulators enable evaluation of process options before wafers are available. Concurrent standard-cell library and block-level design with IC Compiler II and Fusion Compiler enables the use of design-level metrics to select materials, transistor architectures, and process options to meet PPAC targets.
In my mind, Superconducting Electronics (SCE) design is extremely promising and has a huge potential to propel the electronics industry beyond CMOS, enabling a major leap in processing speeds and power efficiency. In some estimates, SCE operating in a cryogenic environment would allow a supercomputer to operate at 100 petaflops of performance for about 200 kilowatts. Today, supercomputers run at 20 petaflops and 10 megawatts.
However, though conventional semiconductor design is highly automated and circuits that can contain more than one billion gates are created with automated design tools, superconductor circuits today can operate at clock speeds in excess of 100GHz but are limited to thousands of gates that must be hand-crafted by experts.
We are working very closely with the Intelligence Advanced Research Projects Activity (IARPA) and leading industry and academic experts to advance EDA tool flows for superconducting electronics—a program they’re calling “SuperTools”. We plan to develop a comprehensive set of tools that increase the scale, efficiency, and manufacturability of these designs to enable advanced high-end computing applications, cryogenically operated low noise sensors and imagers, space applications, and communication links.
The goal of the IARPA SuperTools program is to help make the same design and TCAD tools and quality libraries that drove the semiconductor industry’s growth available for the emerging superconductor industry.