Q: Congratulations on the release of Custom Compiler 2018.09. What are you most excited about in this release?

Aveek Sarkar:

The 2018.09 release introduces several new technologies that help accelerate analog and custom design closure. Custom Compiler was built from the ground up as an open and modern platform, and introduced several innovative and, in many cases, first-in-class capabilities that users appreciate very much. With 2018.09, we continued enhancing the way they can converge on their layout faster, notably through faster interactive usage and newer functions that reduce the time and steps it takes to get a job done. However, I am most excited about the Fusion Technology enablement that brings two of our key signoff products, StarRC and IC Validator, into the Custom Compiler design environment. This allows our users to perform early parasitic extraction even on partial layouts, and perform signoff DRC checks during the design process. The feedback from early adopters has been very positive. We are looking forward to helping designers achieve tighter design/layout collaboration and avoid late-stage design iterations that they otherwise face in their existing legacy workflows.

Q: The recent Custom Compiler news release mentions that you’re seeing strong usage momentum. Can you elaborate on that?

Aveek Sarkar:

Yes, Custom Compiler's customer adoption growth has been quite strong. Our customers consistently tell us they appreciate the improved workflows we’ve introduced, and they find the fundamental capabilities in Custom Compiler to be much more intuitive and flexible. They have realized that migrating to Custom Compiler is very straightforward and, in most cases, engineers are able to bring up their designs with Custom Compiler within a few days. Most importantly, they have validated our position that a Custom Compiler-based flow significantly reduces overall design time and schedules vs. competitive solutions. Additionally, they appreciate the collaborative relationship we maintain through our field and product support teams. Custom Compiler users are our strongest advocates. Based on these factors, we continue to see strong adoption of Custom Compiler across different types of designs, in different regions, and addressing different customer needs. In fact, we doubled our new customer adoption and hit a new milestone of 3,000 users.

Q: What are some of the biggest challenges that you see customers facing in their design process?

Aveek Sarkar:

Custom/analog circuit design has undergone a profound change since I was engaged in it 20 years ago at Sun Microsystems. The design rules, especially those for FinFET technologies, are significantly more complex. Not only are they more complex, they are extremely rigid, quantizing what can and cannot be done. Interconnect parasitics, reliability (especially electromigration and thermal) effects, and manufacturing requirements (DRC) significantly impact the time it takes to close a circuit design; pre-layout simulations diverge significantly from post-layout ones, leading to additional iterations; waiting for the complete layout to converge before performing signoff checks adds considerable delay. These technology challenges by themselves add roughly 3X more time to close a FinFET-based circuit.

In addition, our customers have to deal with organizational and market pressures. Their design teams are geographically dispersed and the need for coordination between the circuit and layout engineers has a significant impact on productivity. Moreover, chips are now increasingly mixed-signal—a digital block often has several custom routes, while an analog block usually contains a digital component. Designing across analog and digital platforms, each with their specific use models, can be a daunting task for most design teams. When considered in combination, the technology, organizational, and market factors can slow down a design process by 3-5X. Clearly, a new methodology supported by a custom design platform that is modern and open is needed to address this widening productivity gap.

Q: What do you think is driving more custom/analog designers to consider Custom Compiler?

Aveek Sarkar:

We have enabled our custom design platform on three pillars—each of which is structured to accelerate designing robust custom circuits. These pillars include Reliability-Aware Verification, Visually-Assisted Layout Automation, and a new Fusion Architecture.

To provide Reliability-Aware Verification we leverage our best-in-class circuit simulation solutions: HSPICE, CustomSim, and FineSim. Depending on the target application, our customers have the choice to use any of these within the Custom Compiler design environment. As designers go from schematic capture to simulation, they appreciate the functionalities we have built into the Simulation and Analysis Environment, especially related to Monte Carlo and PVT corner/sweep simulations, result viewing, data mining, circuit checks, and report generation. At our DAC 2018 lunch event, Sunmin Kim noted that the flow the Samsung team created around Custom Compiler has significantly transformed the way they are managing their simulation workflows.

The second pillar is the cornerstone of our usage model: Visually-Assisted Layout Automation. While the term sounds long, it captures the essence of the value our customers get from Custom Compiler. Through the many workflows and features we have enabled, our customers benefit from significant improvements in layout productivity. In particular, our Symbolic Editor and template-based design (which enables easy reuse of layout work) have been key enablers. Varun Ramaswamy has highlighted how Seagate’s overall design process improved significantly by using these capabilities.

The third pillar is integrating Fusion Technology into the custom design flow. Designers benefit from accessing signoff products like StarRC and IC Validator during the design process, rather than having to wait until the design is complete and clean. The seamless integration between IC Compiler II and Custom Compiler has generated exceedingly positive results—Michael Dierickx from Esperanto stated that they got a 10X productivity boost for their next-generation AI chip.