Cloud native EDA tools & pre-optimized hardware platforms
SNUG World is just a few days away. SNUG World starts and what a fantastic lineup made up of the brightest minds in our industry! With more than 200 technical sessions, panels, and tutorials, across 18 different technology tracks, presented by customers and Synopsys experts covering the latest trends including AI, automotive, cloud, custom-AMS, digital design, IP, low-power design, physical verification, security, signoff and silicon test and analytics.
Things around us are changing rapidly, whether it’s the shift to virtual events or how semiconductor devices are being designed. SNUG World has gone through a revolutionary change. As a virtual experience, it provides an excellent opportunity to share, learn about new technologies, solutions, methodologies, and engage with the technical experts and users.
The Artificial Intelligence (AI) track at the 2021 event offers a real mix of insights and various aspects of AI-based design, the challenges and successes, and in many cases, a much better, efficient way of incorporating strategies and methodologies. This exciting track includes use cases and customer presentations featuring established Synopsys products.
Here is a brief introduction to the AI track sessions.
To kick off the program, I will be moderating an executive panel discussion on AI-driven design. Industry experts from Intel, Qualcomm, Samsung Electronics, and Synopsys will be discussing How is AI Changing the Way We Approach Chip Design? Join us and find out!
Next on the program, Preyas Shah at SimpleMachines will present how they designed a complex, large AI chip and what helped them complete this design quickly and bring it up in the lab in just one week!
Suraj Nair from Intel will talk about the challenges and methodology for best PPA with their AI chip design, many advanced analysis and implementation techniques, and how AI-specific IP is becoming a must-have for many SoCs.
Dhanapathy Krishnamoorthy at Intel will highlight the methodology, approach and how his team achieved best PPA in a much better and energy-efficient manner with an AI Edge inference SoC design.
Day 1 will conclude with Ron Lowman of Synopsys sharing a case study for AI SoC IP and the emerging requirements for fast-changing neural networks and how to enable more competitive, higher performance SoC designs while minimizing time-to-market.
Attendees can enjoy a technical tutorial led by Joe Walston from Synopsys on DSO.ai, Synopsys’ award-winning autonomous artificial intelligence (AI) design system. Tutorial attendees will take away a good understanding of the broad range of design apps and boost in productivity DSO.ai enables throughout the digital implementation cycle.
Milind Mahajan from Intel will then showcase how AI-driven design with DSO.ai is used to maximize PPA and simplify design optimization, driving towards PPA auto-convergence in real-life production environment.
Chang-Ho Han at Samsung Electronics will present a detailed case study on AI-driven design space optimization and how Samsung realized benefits of the AI-driven design approach, both to push PPA and to perform design-technology co-optimization (DTCO).
Rohit Sinha of Intel will share how he applied machine learning algorithms to identify the root cause of issues which could result in a huge number of violations in asynchronous designs, and how to minimize the debug turnaround time and effort.
Intel's Santanu Kundu will bring the AI session to an exciting conclusion with a presentation about his success with unsupervised machine learning-based root cause analysis to reduce debug turn-around-time for low-power issues. He will discuss the methodology and showcase the benefits witnessed at different phases of the designs.