Tools for 3rd Party FPGA Prototyping Boards

FPGA-based prototyping is growing in popularity as it allows ASIC design teams to meet their development schedules for hardware and software enabling the longest time in market.

Synopsys' FPGA-based Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Together, our suite of tightly integrated and easy-to-use HAPS hardware plus ProtoCompiler dramatically accelerate software development, hardware/software integration and system validation from individual IP blocks to processor subsystems to complete SoCs.

In addition to the fully integrated FPGA-based prototyping solution based on HAPS hardware and ProtoCompiler, Synopsys also provides a suite of tools for FPGA-based prototypers building their own boards, which includes Certify, Synplify Premier, Synphony Model Compiler and Identify RTL Debugger.

FPGA-based prototyping tool suite for 3rd party boards

Synopsys FPGA-based prototyping tool suite for 3rd party boards

  • Synplify Premier – Provides fastest time to initial hardware and turn-around time, highest timing QoR with smallest area and integration with DesignWare and VCS
  • Identify – Fast and easy debug with simulator like visibility and easy to use triggering/signal tracing
Multiple and single FPGA-based prototyping flow for 3rd party boards

Multiple and single FPGA-based prototyping flow for 3rd party boards

Synplify Premier provides ASIC and SoC designers with several features that help accelerate development of a semiconductor prototype. One of the first challenges faced by designers is the replacement of non-FPGA-based portions of the designs, such as memories, clock configurations and ASIC test circuitry. Synplify Premier provides an easy methodology for handling side files in addition to parsing multiple language formats and constraints files. The next challenge is the importing and handling of 3rd party, Synopsys and internally developed IP, which Synplify Premier automates to significantly increase productivity. Finally, Synplify Premier automates clock conversion so that an ASIC design can fit into the clock structures of an FPGA.

For more Information on ASIC Conversion, download the white paper.