By Manuel Mota, Technical Marketing Manager, Synopsys
For designers using analog-to-digital converters (ADCs), the latest and greatest architectures can hold the key to reducing power, cutting area and increasing performance. The most recent advance is the introduction of Successive-Approximation Register (SAR)-based architectures for high speed, high resolution ADC implementations, due to their potential benefits in terms of power and area reduction and also their relative immunity to the “analog-unfriendliness” of advanced process nodes (28-nm) and beyond (16/14-nm).
The SAR architecture digitizes the input signal step-by-step by running a successive approximation algorithm and determining each bit in successive clock cycles until the complete conversion is finalized. This architecture reuses the same hardware for each step and requires a high clock rate to complete the conversion before the next sampling instant. For example, the SAR algorithm to determine 10-bits may take 10 or more clock cycles to complete, therefore the clock rate for this ADC needs to be 10 or more times higher than the rate at which samples are taken for conversion. Consequently, this architecture has traditionally been limited to low-speed and medium- to high-resolution applications.
Figure 1 shows the basic block diagram of a SAR ADC including a sample-and-hold (S&H), a comparator, a digital-to-analog converter (DAC) and a logic block (SAR). The input signal (Vin) is stored on the sample-and-hold and is successively compared to the output of the DAC, whose input codes are set by a logic block depending on the result of the previous comparisons.