ARC Processor Summit 2017 Proceedings

Your Embedded Edge Starts Here

Synopsys' ARC® Processor Summit 2017 offered 29 sessions focusing on the latest technologies and trends in embedded processor IP, software, programming tools and applications. Browse the presentations, or select a specific track:

Keynote Address


How AI, Deep Learning and Machine Perception are Changing Our World
Jeff Bier, Founder, Embedded Vision Alliance and President, BDTI

Just a few years ago, it was inconceivable that everyday devices would incorporate human-like sensory perception. Now it’s clear that sophisticated perception will soon be ubiquitous in many types of systems. How soon? Faster than you might think, thanks to three key accelerating factors.

In a very short time, we're seeing roughly a 10X improvement in cost-performance and energy efficiency at each of three layers: algorithms, software techniques, and processor architecture. Combined, this means that we can expect roughly a 1,000X improvement. So, tasks that today require hundreds of watts of power and hundreds of dollars' worth of silicon will soon require less than a watt of power and less than a dollar's worth of silicon. This will be world-changing, enabling even very cost-sensitive devices, like toys, to incorporate sophisticated visual perception.

In this talk, I’ll show how innovators across the industry are delivering this 1,000X improvement very rapidly. I’ll also explain the relationships between artificial intelligence, machine learning, deep learning, and machine perception. Finally, I’ll illustrate through examples how these technologies are transforming many types of products, and highlight important challenges that remain.

Hardware Track


10:30 a.m. - 11:00 a.m. 
Living on the IoT Edge - Doing More with Less 
Fergus Casey, R&D Director, Synopsys

The Internet-Of-Things (IoT) market is causing the focus of IC design flows to shift from increasing performance to reducing power in order to meet the demands of battery-operated devices. For many of these applications, the opportunities to replace (or even recharge) batteries are limited. Power-efficient processors are critical to reducing the overall power profile required by IoT ICs. This presentation will provide an overview of ARC EM processor features and techniques to increase energy efficiency, extending your IoT edge products’ life expectancy in the wild.

11:00 a.m. - 11:30 a.ml
Accelerating DSP Algorithms using ARC Processor EXtension (APEX) Technology in ARC EM9D/11D Processors 
Abhishek Bit, CAE, Synopsys

Code efficiency and performance are critical requirements for modern digital signal processing systems. This session will present some key techniques and processor architecture features that can be used to accelerate typical digital signal processing algorithms. DSP examples and optimization strategies will be presented for the DesignWare ARC EM9D and EM11D Processors. ARC Processor EXtension (APEX) technology can accelerate such algorithms, significantly reducing memory footprint. The performance benefits obtained by using APEX can be further leveraged using the XY memory architecture on ARC EM9D and EM11D Processors.

11:30 a.m. - 12:00 p.m.
IoT Demo Platform: Foundry, IP, Services 
John Zhuang, CTO, Brite Semi

The IoT market is filled with IoT platforms, many saving customers’ development time. Experience has proven that while reducing time to market is important, it is not the only thing required to build a successful platform. Brite Semi will discuss a new IoT Platform developed in a collaboration with SMIC and Synopsys that enables OEMs, system integrators, and startups to leverage a platform with innovative technologies from foundry, to IP & subsystems, and full spec to chip services.

12:00 p.m. - 12:30 p.m. 
Using Design Time Analysis to Test Security Countermeasures Implemented in ARC SEM Processors 
Jasper van Woudenberg, CTO, Riscure North America

Products in markets including automotive, IoT and payment need high levels of security. One of the main challenges in creating secure systems is to keep encryption keys secure and difficult to derive by an adversary. Side-channels attacks, such as power consumption analysis on data dependent computations, are a known attack to gain access to these encryption keys. Currently testing of side-channel resistant designs requires testing to be performed on the actual silicon. This presentation describes a new tool and methodology using Synopsys’ simulators with Riscure’s side channel analysis tool to test side-channel countermeasures’ effectiveness on an ARC SEM processor prior to implementing them in silicon. The use of this tool will result in fewer tape-outs, lower cost, and shorter time to market.

1:30 p.m. - 2:30 p.m. 
No More Excuses: Secure Your SoC from IP Building Blocks to End-to-End Systems 
Ruud Derwig, Software and Systems Architect, Synopsys

Despite the cybersecurity media hype, security is still an afterthought in many designs. Instead of proactive, differentiating, future-proof security designs, security is generally considered a nuisance forced by regulations or an ad-hoc solution triggered by security breaches. Lack of knowledge, additional cost, and complexity are the typical excuses used. The resulting vulnerabilities range from simple software misconfiguration to more complex vulnerabilities such as side-channel leakage. To address these security challenges Synopsys offers a scalable range of security IP building blocks that offer the combined efficiency and security required for IoT applications. This presentation will describe how Synopsys reduces complexity and mitigates knowledge roadblocks by pre-integrating hardware and software IP into a Secure Subsystem that seamlessly fits into already standardized end-to-end security solutions like embedded SIM. 

2:30 p.m. - 3:00 p.m. 
Ultra-low Power 3D Micro-GPU for IoT Devices with a DesignWare ARC EM5D Processor 
Iakovos Stamoulis, CTO and Co-Founder, Think Silicon

The emerging Internet-of-Things market, with display devices limited in area, performance, memory, thermal dissipation and battery capacity is adding design challenges for engineers. The end-user is expecting the same fluid interaction and high–quality graphical-user-interface (GUI) experience known from their smart phones and tablets. Synopsys and Think Silicon developed a prototype sporting an ARC EM5D Processor with a NEMA®-GPU including NEMA® |GFX-API. The solution is aimed for developers to rapidly implement high-quality 3D graphics in connected ultra-low-power wearables and embedded devices with reduced risk and cost.

3:00 p.m. - 3:45 p.m. 
Play it Safe with the ARC EM Safety Island 
Srini Krishnaswami, ASIC Digital Design Engineer, Synopsys

Developing ISO 26262 certified safety-critical automotive systems has created a new set of processing challenges for IC suppliers. This presentation will provide an overview of the key challenges to achieve ASIL D certification in a complex SoC and how ASIL D ready certified ARC EM Safety Island IP together with Synopsys STAR memory and logic test solutions can accelerate the development, verification, and certification process of automotive SoCs, reducing the overall safety investment within your SoC.

4:00 p.m. - 4:45 p.m. 
Machine Learning for Low-power IoT Devices 
Anatoly Savchenkov, Software Engineering Manager, Synopsys

Use of machine learning algorithms in IoT is proliferating dramatically. Multisensory context awareness, natural human to machine interfaces, and decision-making in various disciplines such as mechanical fault detection and personal healthcare are just a few examples of applications that would not be possible without these algorithms. The technology is migrating from traditional cloud-based services to local devices for better efficiency, autonomy and privacy. The multitude of artificial neural network classes and constantly increasing model complexity present a number of challenges for systems developers. This session presents approaches to solving the challenges of using machine learning technologies in low-power IoT devices.

4:45 p.m. - 5:30 p.m. 
Enabling Performance-intensive RISC and DSP Applications with New Superscalar ARC HS4x/D Processors 
Carlos Basto, ASIC Digital Design Engineer, Synopsys 

Next-generation embedded applications such as human-machine interfaces for virtual reality require very high performance and a combination of RISC and DSP processing. Synopsys’ new HS4x/D processor family is designed to deliver this performance. These new high-performance processors deliver multi-issue, multi-core capabilities and combine RISC and DSP processing to maximize performance while minimizing power consumption, memory requirements and system resources. This session will look at the capabilities of the new family and how they can be used to address performance-intensive mixed-signal embedded applications. 

Software Track


10:30am - 11:15am
Detecting and Avoiding Common RTOS-related Bugs 
Niclas Lindblom, Field Application Engineer, Percepio AB

Real-time operating systems (RTOSes) are increasingly common in the development of embedded software, due to increasingly complex and connected applications that often benefit from multi-threading. However, introducing an RTOS may bring new types of software problems related to timing, synchronization and resource usage; elusive bugs that may slip out into production code. This talk will discuss common RTOS-related bugs, why they occur and “best practices” in embedded software design for avoiding them. We also present techniques and tools for visualization and analysis of RTOS-related issues, to provide better insight and thereby facilitate debugging and general understanding of the runtime events.  

11:15 a.m. - 11:45 a.m. 
The Zephyr Project: This Year, Next Year
Kate Stewart, Sr. Director of Strategic Programs, Linux Foundation

Zephyr is an upstream open source project for devices where Linux is too big to fit. This talk will overview the progress we've made in the first year towards the projects goals around incorporating best of breed technologies into the code base, and building up the community to support multiple architectures and development environments. We will share our roadmap, plans and the challenges ahead of the us and give an overview of the major technical challenges we want to tackle in the next year.

11:45 a.m. - 12:30 p.m.
Programming DSP Processors Efficiently and with Ease 
Pieter van der Wolf, Principal Product Architect, Synopsys

The ARC EM and HS processor families both offer processors with the ARCv2DSP ISA extension to support a wide range of DSP applications. These DSP processors come with an advanced tool suite, including a powerful DSP compiler, to support C-level programming of DSP applications. In this presentation we show how excellent results, in terms of high performance and small code size, can be achieved with high-level DSP programming. Ease of programming is also supported with an extensive library of DSP functions. The high-level programming enables software compatibility across different ARC DSP processors.

1:30 p.m. - 2:00 p.m.
Sound Processing in Smart Home Devices – A System Approach 
Robert Schrager, Director of Sales and Marketing, Alango Technologies

Speech, as the most natural way we express ourselves, has tremendous potential as a method of human-machine interface. Speech recognition technologies have improved significantly but are still dependent on factors that influence the signal to “noise” ratio. During the last three years Alango, a leading provider of speech and audio enhancement DSP technologies, has accumulated significant practical experience in integration of front-end speech enhancement and speech recognition. In this presentation we will discuss all aspects of signal processing in Smart Home devices, including multi-microphone beamforming, echo cancellation, as well as keyword recognition and the computational resources necessary to perform such tasks. We’ll discuss both technology and system aspects. Additionally, we will share our vision for the voice interface of the future and discuss R&D topics to make it a reality.

2:00 p.m. - 2:30 p.m.
OpenThread: Tales from the Front Lines 
Francois Bedard, Senior R&D Manager, Operating Systems and Open Source Software, Synopsys

The Thread protocol from the Thread Group has seen strong adoption as an industry standard for Smart Home connectivity. In this talk we will look into the capabilities of the Thread protocol and share experiences from porting the OpenThread open source implementation of the Thread specification protocol stack to the ARCv2 architecture, targeting the ARC EM Starter Kit platform.

2:30 p.m. - 3:00 p.m. 
Building an Embedded Linux Distribution for Your ARC Platform 
Alexey Brodkin, Senior Software Engineer, Synopsys

Linux is a robust operating system that provides a rich set of capabilities to embedded systems. However, building and maintaining a Linux distribution for embedded platforms can seem like a daunting task to the first-time user. In this session, an expert from our open source team will review several options and provide tips and insights for successfully creating and maintaining your own embedded Linux distribution.

3:00 p.m. - 3:45 p.m.
Full-featured Hardware Platforms to Accelerate Your ARC Software Development 
Wido Kruijtzer, Senior Manager, ASIC Digital Design, Synopsys 

Starting software development early is a requirement for meeting the ever-shortening development cycles for complex SoC projects. Having the right hardware platform for that purpose, along with the associated software support, is key to achieving success. Synopsys provides a variety of platforms for software development on ARC processors. The platforms range from FPGA-based starter kits to full-speed silicon-based platforms with a rich set of peripherals and comprehensive extensibility options. The platforms are supported by the tools and software necessary to develop bare-metal, RTOS and, in the case of ARC HS processors, Linux and other high-end applications. In this session, we will provide an overview of several of the available platforms and examine the software support available to speed application development on ARC.

4:00 p.m. - 4:30 p.m.
Secure, Java-programmable Ecosystem on ARC SEM Cores for End- Point Devices with Sensors and Data Processing Capabilities 
Mikhail Friedland, CEO & President, jNet ThingX Corp

When creating distributed IoT control systems, we rely on edge devices or end-points. But, are these devices secured against cyber-attacks? Design teams working on these projects require multi-discipline engineering talent that includes embedded hardware and software engineers, protocol designers, and crypto experts. This session presents a software development environment and platform that accelerates time-to-market by removing these complexities and has helped secure billions of SIMs, smart cards and ePassports. It provides a secure Java-programmable system running on ARC SEM cores to power IoT devices with sensor-awareness and multi-protocol SoC connectivity.

4:30 p.m. - 5:00 p.m.
The Secrets of Building Secure IoT Edge Devices: ARC SecureShield 
Ruud Derwig, Software and Systems Architect, Synopsys

Developing bug-free software is complex and costly. Buffer overruns and other software errors still rank high in Common Weakness Enumeration (CWE) statistics. SecureShield™ cannot stop users from writing vulnerable software, but it helps contain the resulting vulnerabilities. Software in a device comes from sources with different trust levels: internal development, external suppliers, open source, and maybe even end-users. Different software modules also have different protection requirements. SecureShield technology helps isolate these different classes of software and uses least-privilege access control to protect system resources, optimized for low power/cost IoT edge devices. This presentation introduces SecureShield, provides an update on latest features, and demonstrates these features with the Agile Crypto Platform solution jointly developed by InfoSec Global and Synopsys.

5:00 p.m. - 5:30 p.m.
Easing Trace Debug in SoCs with Multiple Processor Architectures 
Fergus Casey, R&D Director, Synopsys

ARC Real-Time Trace (RTT) is an efficient way to capture the behavior of a program: not only instruction trace, but register and memory changes as well. Trace data can be captured at high rate and uploaded to the debugger at Gigabit Ethernet speeds. 

The ARC trace portfolio eases the hardware integration burden in SoCs with heterogeneous processor architectures by reducing trace logic and pin overhead in designs that include a mix of ARM and ARC processors, while also streamlining the debug experience for the firmware teams. This presentation explains the ARC trace architecture together with CoreSight support using the Lauterbach Trace32 debug platform.

Embedded Vision Track


10:30 a.m. - 11:30 a.m. 
Eliminate Processor Bottlenecks with Tightly Integrated Processing Units for Embedded Vision 
Gordon Cooper, Product Marketing Manager, EV Processors, Synopsys

As embedded vision processing performance requirements increase and power and area goals remain aggressive, embedded engineers looking for the most optimized performance and power solution for vision are turning toward high-performance embedded vision processors tightly coupled with dedicated neural network engines. This presentation will describe how embedded vision processors, offering a combination of tight integration and scalability, can efficiently support high performance vision applications such as surveillance, autonomous driving and augmented reality.

11:30 a.m. - 12:00 p.m. 
New and Emerging Standards for Embedded Vision Programming 
Radhakrishna Giduthuri, Member of OpenVX and NNEF Working Groups, AMD

The landscape of APIs for accelerating vision and neural network software using specialized processors continues to rapidly evolve. Many industry-standard APIs, such as OpenCL and OpenVX, are being upgraded to increasingly focus on deep learning, and the industry is rapidly adopting the new generation of low-level, explicit GPU APIs, such as Vulkan, that tightly integrate graphics and compute. Some of these APIs, like OpenVX and OpenCV, are vision-specific, while others, like OpenCL and Vulkan, are general-purpose. Some, like CUDA and TensorRT, are vendor-specific, while others are open standards that any supplier can adopt. Which ones should you use for your project?

12:00 p.m. - 12:30 p.m. 
Automated Parallel Kernel Processing using OpenVX 
Vineet Gupta, R&D Engineer, Synopsys

OpenVX is the software framework that combines the different heterogeneous components of the embedded vision system -- including scalar processing, vector DSP processing and deep learning with a CNN accelerator. This presentation will introduce OpenVX using an example embedded vision solution.

1:30 p.m. - 2:00 p.m.
OpenCL C for Efficient Programming of SIMD Machines 
Seema Mirchandaney, Software Engineering Manager, Synopsys 

This presentation will focus on the benefits and ease of programming vision-based kernels using the key features of OpenCL C. The language extensions that allow programmers to take advantage of hardware features typical of embedded vision processors, such as wider vector widths, sophisticated accumulator forms of instructions, and scatter/gather capabilities, will be described. Advanced topics, such as whole function vectorization support available in the compiler and the benefits of hardware support for predication in the context of lane-based control flow and OpenCL C will also be covered.

2:00 p.m. - 2:30 p.m.
Efficient Acceleration of OpenCV on Next-generation EV6x Vision Processor 
N Vinith Kumar, Senior Technical Lead, PathPartner

OpenCV is an open source library of 2500 vision algorithms that help build vision applications. This presentation will discuss which OpenCV algorithms are most important for embedded vision and will cover optimization techniques for getting the best performance out of these library functions. 

2:30 p.m. - 3:00 p.m.
Scene Classification: Deep Learning for Mobile
Toshi Torihara, Vice President, Morpho US, Inc.

There is a growing need for neutral network configurations that are suitable for edge processing using Deep Learning technology in the embedded system industry, and demand for a reduction in computing load has also been increasing. This presentation will discuss the optimization of Morpho's image recognition engine on Synopsys's DesignWare® EV6x Vision Processors to realize high performance and real-time image processing in system-on-chip products. Morpho capabilities include image enhancement technology which combines deep learning and computational photography.

3:00 p.m. - 3:45 p.m. 
The Evolving Neural Network: Understanding and Applying the Latest CNN Techniques
Gordon Cooper, Product Marketing Manager, EV Processors, Synopsys

The advances in computer vision research are continuing at a fast pace with rapid transitions from research topic to a implemented technology. This presentation will discuss the current and near future expectations for the evolving deep learning and embedded vision markets. Broader use cases for CNN will also be discussed -- like in radar and audio applications -- as well as other neural network techniques and applications involving RNNs.

4:00 p.m. - 4:30 p.m.
Progressive Pruning of CNNs to Reduce Memory Size and Bandwidth 
Anshu Arya, Solution Architect, MulticoreWare

Research into CNN algorithms has evolved from finding the highest accuracy, to finding the highest accuracy with the least amount of computations. This presentation will discuss the latest techniques for graph pruning including a practical example and benchmark improvements. 

4:30 p.m. - 5:30 p.m.
Practical Considerations for Mapping a CNN Graph to an Embedded Vision Processor 
Bo Wu, CAE, EV Processors, Synopsys

In this presentation, you will learn the development flow and implementation considerations for moving from an academic CNN/deep learning graph to a commercial embedded vision design. The presentation will use practical examples that highlight the latest CNN graph mapping tool capabilities, including dispatched processing and pruning/compression. You will also learn about the cost vs. accuracy trade-offs of CNN bit width, balancing internal memory size and external memory bandwidth, and the importance of keeping data local to the CNN processor to improve bandwidth. Key deep CNN/learning benchmarks will be discussed including VGG16, Yolo, Denoiser, and more