ARC Processor Summit'16 Proceedings | DesignWare IP | Synopsys

ARC Processor Summit 2016 Proceedings

Your Embedded Edge Starts Here

Synopsys' ARC® Processor Summit 2016 offered 23 sessions focusing on the latest technologies and trends in embedded processor IP, software, programming tools and applications. Browse the presentations, or select a specific track:


Keynote Address: IoT Standards Wars: Designers Caught in the Middle?
Linley Gwennap, Principal Analyst, The Linley Group

The Internet of Things is not a single market but rather a plethora of things, each with its own technology requirements and target customer. As a result, many new standards are being proposed, but these standards may meet the needs of only certain types of IoT devices. This presentation will discuss standards for communication protocols, software, and services for IoT devices, helping to sort out which are applicable and which are most likely to succeed. It will also address technologies for securing the IoT and other trends affecting SoC design.

Hardware Track

Addressing the Evolving Processing Needs of IoT Applications
Rich Collins, Product Marketing Manager, Synopsys

As IoT device implementations mature, in addition to meeting the integration and low-power demands of battery operated IoT applications, designers are looking to address the increasing processing needs of these applications. Sensor fusion has evolved into the broader scope of data fusion, where voice recognition, audio playback, face detection and basic gesture recognition complement the sensor processing functions on an IoT device. Ensuring secure operation and transmission of data is also critical for IoT devices supporting fitness and health applications, financial transactions and e-government products. Efficient processors and pre-verified, SoC-ready subsystems simplify the development of chips targeting ever more complex IoT applications with dedicated features addressing the evolving security and processing needs of these new IoT devices.

To manage this onslaught of new functionality, IoT edge devices increasingly require higher bandwidth analysis to be performed locally (on-chip). Synopsys and Renesas have worked together to build a new reference design supporting power efficient data fusion processing with higher performance MONOS embedded flash technology to provide the ideal power/performance trade-offs required for the next generation of IoT devices.

APEX: Using ARC Processor Custom Extensions to Differentiate Your SoC 
Joep Boonstra, Sr. Staff Architect, Synopsys

In a highly competitive semiconductor market, it is increasingly important to be able to quickly and easily differentiate your device. This session will introduce ARC Processor EXtension (APEX) technology, which can be used to extend the instructions and register set of the CPU as well as add tightly coupled peripherals and custom interfaces to the core. It will also include real-world examples and recent additions to optimize performance for complex extensions while retaining a simplified interface.

IoT Security: Protecting Your SoC from Malicious Physical and Software Attacks 
Ruud Derwig, Software and Systems Architect, Synopsys

Security is of critical importance to IoT applications. This session will present threats to IoT security, and hardware-rooted processor security solutions that defend against these. Both logical (software) as well as physical (hardware) attacks will be addressed. Special attention will be given to countermeasures for Side Channel Analysis (SCA) attacks, or non-invasive physical attacks that reconstruct secret cryptography keys from information leaked from an SoC’s power consumption or electromagnetic radiation. Without countermeasures, it can be surprisingly easy to obtain these secret keys, and therefore SCA countermeasures are required by more and more IoT standards.

Maximizing Embedded Performance with Multicore Processors 
Kulbhushan Kalra, Manager, ASIC Digital Design, Synopsys

The availability of specialized high-performance processors that support multicore implementation is changing high-end embedded applications. With limitations on maximum clock frequencies and power consumption, multicore processors are making it possible to address advanced applications with significant increases in performance and a minimal increase in power consumption. Processors designed for multicore implementation also support the variety of needs that arise in embedded applications and enable easy upgrade to higher performance for future designs. This presentation details the architecture of a processor family that has been designed specifically to address the requirements of high-performance, multicore embedded applications.

Designing with Processors in Safety-Critical Automotive Applications 
Fergus Casey, Senior R&D Manager, Synopsys

As more SoC designs are used in electronic systems deployed in safety-critical applications, functional safety is an important consideration in system architecture and verification methodology. Security is also a key concern for connected cars and should be a consideration in safety applications. This session will outline the key requirements for ISO 26262 and security as they relate to processor IP and demonstrate how safety-critical IP and SoC developments can be greatly accelerated through the use of out-of-the-box safety ready IP, together with advanced verification qualification tools and methodologies.

Achieving 7X Better Power Efficiency with a Unique Sub-Threshold Technology Implementation of an ARC EM5D Processor Based Subsystem 
Uzi Zangi, CEO & Co-founder, PLSense

The emerging Internet-Of-Things (IoT) market is causing the focus of IC design flows to shift from increasing performance to reducing power in order to meet the demands of battery operated devices to increase their battery lifetime. PLSense has developed comprehensive technology for sub-threshold libraries and design flows, which enables the design of ICs that can operate at voltages as low as 0.45V while significantly improving battery life compared to existing solutions. As part of this technology, PLSense implemented an MCU chip fabricated on the TSMC 40-nm ULP process using Synopsys’ DesignWare® Smart Data Fusion IP Subsystem. This presentation will describe the implementation of the MCU using the sub-threshold technology and show how it achieved up to 7X better power per MHz than comparable solutions.

Designing a Next-Generation PCI Express-Based Enterprise SSD Solution using ARC Processors 
Tao Wang, Chief Engineer, Digital Verification, Starblaze

High performance, small form factor and low power consumption are important considerations in the design and selection of an SSD product. Enterprise SSD products are also characterized by a very high “mean time between failures” (MTBF) value, high data integrity and end-to-end data protection. Enterprise SSD products are expected to be used in heavy workload environments and still deliver high performance. This presentation addresses the challenges and requirements for the underlying CPU in an Enterprise SSD solution. It highlights how a multi-core ARC HS Processor and ARC EM Processor based SoC proves to be the ideal choice for the Enterprise SSD product, and explains how ARC processors can easily meet key Enterprise SSD application requirements.

Software Track

Zephyr: Creating a Best-of-Breed, Secure RTOS for IoT
Kate Stewart, Sr. Director of Strategic Programs, Linux Foundation

Zephyr is a new upstream open source project for places where Linux is too big to fit. The starting point for Zephyr is from a commercial project that has been made open for the community to evolve and enhance into a secure best-of-breed RTOS for the IoT ecosystem. This talk will provide an overview of how we are incorporating leading technologies into the code base, and building up the community to support multiple architectures and development environments.

Optimizing Memory in IoT and Embedded Applications 
Francois Bedard, Sr. R&D Manager, Operating Systems and Open Source Software, Synopsys

IoT edge devices need to provide required performance at ultra-low power and low cost to enable ubiquitous deployment. Both SoC silicon area and memory usage must be minimized to reduced overall system cost. In this session you will learn how to deploy an embARC-based IoT edge application software stack in a fraction of the memory required.

Using a Qualified Compiler to Develop Safety-Critical Software 
Mitesh Shah, Manager, Software Engineering, Synopsys

The MetaWare Compiler has been qualified for use as the compilation toolchain when developing safety-critical applications according to ISO 26262. It can be used for components with a maximum Automotive Safety Integrity Level ASIL D. This session will describe how to use the compiler and the accompanying documentation in order to be in compliance with these important safety standards.

Sensor Processing for Smart Home and IoT 
Dave Karlin, VP of Strategy, Hillcrest Labs

Many emerging applications, such as virtual reality, augmented reality, and robotics have unique sensor processing requirements and require an optimum combination of hardware and software. This presentation will focus on how Hillcrest Labs’ specialized software and Synopsys’ ARC processors can enable high-accuracy, low-power sensor processing for Smart Home and a wide range of IoT applications.

Using the MPU with an RTOS to Enhance System Safety and Security 
Steve Ridley, Principal Software Engineer, WITTENSTEIN

For safety-critical software, it is necessary to understand the requirements of the application, be able to demonstrate that the requirements have been met and prove that all the code is necessary and tested. This disciplined approach to engineering is the starting point for safety applications. Run time monitoring of an application and its underlying hardware is also commonplace. One hardware peripheral that can help with this is a Memory Protection Unit (MPU). Correct configuration of the MPU can allow software bugs or corruption to be trapped before damage can occur; however, active management of the MPU in conjunction with an RTOS allows meaningful task/thread isolation of mission critical parts of the application. This presentation discusses methods of achieving partitioning and error detection using the MPU.

Software Development Kits for Simplifying Security Implementation 
Mike Borza, Member of Technical Staff, Security IP, Synopsys

Secure Boot can greatly enhance the security of an embedded system by verifying that the code being loaded and executed has not been unknowingly or maliciously modified. This presentation will cover the Secure Boot Software Development Kit, which allows developers to implement Secure Boot systems using software-only constructs or with Synopsys offload engines. It will also provide an overview of Synopsys cryptography software, which includes a comprehensive suite of widely used crypto algorithms and simple plug-in modules to transparently support hardware acceleration or offload.

A Lightweight Trusted Execution Environment for IoT Edge Devices 
Ruud Derwig, Software and Systems Architect, Synopsys

Developing completely bug-free software is complex and costly, but the bugs that remain pose a security threat when maliciously exploited. In addition, software in a device comes from sources with different trust levels: internal development, external suppliers, open source, and maybe even end-users. The standard solution for mixed-criticality components is isolation. For security this means a securely shielded Trusted Execution Environment. For low power/cost IoT edge devices, however, a separate secure processor or full virtualization is not an option. This session presents a lightweight solution to efficiently shield secure from non-secure software on a single microcontroller.

Pervasive Authentication for IoT: ARC Processors with PUFs 
Pim Tuyls, CEO, Intrinsic-ID

This presentation will explain Physical Unclonable Functions (PUF) technology and how it can be used for authentication and encryption in IoT and embedded systems. Also, it will cover how PUF is integrated into the ARC architecture and how it interacts with other security features and crypto accelerators. The presentation includes an example using PUF to authenticate a sensor to the cloud and guidance for designers who need to find a balance between performance, code size, and gate count.

Embedded Natural Language Voice Interfaces 
Kashif Kahn, CEO, Sage Senses

Advances in machine learning and embedded engineering technologies now make it possible to design and implement sophisticated natural language voice interfaces on ordinary microcontrollers. Embedded voice interfaces address connectivity, bandwidth, latency, energy, and/or privacy issues associated with cloud-based speech systems. They can be utilized either as a complement (eg. backup) or as an alternative to cloud-based speech systems. For most “command-and-control” applications in consumer and industrial domains, a natural language voice interface can be deployed on a microcontroller with less than 1 MB of RAM+ROM and 200 MHz CPU. Further, a developer can train a sophisticated Natural Language Understanding (NLU) engine for his voice interface with a small amount of data.

The Case for Trace 
Hugh O’Keeffe, Engineering Director, Ashling

Embedded debugging techniques have evolved from print to the more advanced techniques used today including run-control debug and real-time trace. This presentation will explain these two approaches and discuss the advantages of real-time trace and why it is suitable for validating and debugging complex systems including multicore architectures based on DesignWare ARC Processors. Specific use-cases will be presented showing how to use real-time trace to identify and solve common errors.

Embedded Vision Track

Advanced Vision Capabilities for Next-Generation SoCs 
Bo Wu, Embedded Vision Applications Engineer, Synopsys

The availability of specialized high-performance processors is making it possible to integrate vision capabilities into SoCs, giving them the ability to see and interpret their surroundings. These heterogeneous multicore processors support HD resolutions with low power consumption and include specialized vision engines to improve accuracy. Supporting these processors are a range of tools including OpenVX™, OpenCL™, and OpenCV that greatly improve developmental productivity. This presentation details the architecture of an embedded vision processor family and the open source vision tools used to program and ensure efficient resource utilization of the heterogeneous multicore platform.

Computer Vision 2.0: Where We Are and Where We’re Going 
Jeff Bier, Founder, Embedded Vision Alliance and President, BDTI

Computer vision has rapidly transitioned from a research topic to a mainstream technology with applications in virtually every sector of our economy. But what we are seeing today is just the beginning. This presentation provides an insider's view of the state of embedded vision technology and applications today, and predictions on how the field will evolve in the next few years. It will explore the impact of game-changing technologies such as deep neural networks, and highlight new products and applications that illuminate what we can expect from visually intelligent devices in the near future.

The Vision API Landscape 
Neil Trevett, President, Khronos and Vice President, NVIDIA

The choice of hardware acceleration APIs for parallel computation and vision processing is complex and rapidly evolving. Many of the industry-standard APIs such as OpenCL and OpenVX have been upgraded, while the industry begins to adopt the new generation of low-level, explicit GPU APIs, such as Vulkan, that tightly integrate graphics and compute. Some of these APIs, like OpenVX and OpenCV, are vision-specific, while others, like OpenCL and Vulkan, are general-purpose. Which one(s) should you use for your project? This presentation provides an update of the landscape of APIs for vision software development, explaining where each one fits in the development flow. It also highlights where these APIs overlap and where they complement each other, and previews some of the latest developments.

Using the OpenCL C Kernel Language for Embedded Vision Processors 
Seema Mirchandaney, Manager, Software Engineering, Synopsys

OpenCL C is a programming language that is used to write computation kernels. This presentation will focus on the benefits and ease of programming vision-based kernels using the key features of OpenCL C. The language extensions that allow programmers to take advantage of hardware features typical of embedded vision processors, such as wider vector widths, sophisticated accumulator forms of instructions, and scatter/gather capabilities, will be described. Advanced topics, such as whole function vectorization support available in the compiler and the benefits of hardware support for predication in the context of lane-based control flow and OpenCL C will also be covered.

Visual Perception and Computer Vision for Surveillance and Automotive 
Vangelis Vassalos, Sr. Embedded Software Engineer, Irida Labs

Irida Labs offers an extensive computational photography, vision perception and analytics portfolio of optimized IP cores, applicable to the demanding security, surveillance and automotive markets. Irida Labs has optimized OpenVX-based versions of its video stabilization, low-light video enhancement and de-noise IP cores, ViSTA-EV, EnLight-EV and DeNoise-EV for the DesignWare EV processors, with a motion profile for surveillance and automotive. This presentation will show the profiling results of single-core and multi-core implementations of these cores and will discuss future plans for porting Irida Labs’ face recognition and scene analysis IP cores, using the DesignWare EV processor object detection engine for CNN-based processing.

Targeting CNNs for Embedded Platforms 
A.G. Karunakaran, Founder and CEO, MulticoreWare

MulticoreWare designs convolutional neural network (CNN) applications that target embedded platforms and execute within strict compute, memory, and power constraints. This presentation will discuss the challenges encountered in developing CNNs for embedded platforms and some of the techniques used to target modern embedded designs.

Speaker Bios

Francois Bedard is a senior R&D manager in Synopsys’s Processor Solutions team with over 25 years of embedded software development and leadership experience across several areas including telecommunications, high performance networking applications and systems development, embedded multi-core architectures and open source software including Linux and GNU Tools. Francois holds a bachelor’s degree in electrical engineering from McGill University in Montreal, Canada.   


Jeff Bier is president of BDTI. For over 20 years BDTI has helped hundreds of companies choose the right processors and develop optimized software for demanding applications in audio, video and computer vision. Jeff also oversees the Embedded Vision Alliance, a partnership of 50 technology companies that works to enable the widespread use of practical computer vision. Jeff is a frequent keynote and invited speaker at industry conferences, and writes the popular monthly column “Impulse Response.”   


Joep Boonstra brings 20+ years of experience to his role as senior staff DSP architect at Synopsys. Prior to joining Synopsys, Joep held senior principal roles at NXP Semiconductors and Virage Logic, working in domains like IP design for re-use, systems-on-a-chip, networks-on-chip and off-chip interconnectivity standards. Joep has an MSc in Electrical Engineering from the University of Twente, the Netherlands.   


Mike Borza is a member of the technical staff with Synopsys’ security IP team, and has more than 20 years of experience in security system engineering, and safety critical system engineering before that. He is the founder and CTO of Elliptic Technologies, which was acquired by Synopsys. Mike has been an active contributor to the Security Task Group of IEEE 802.1; was an editor of the 802.1AR Secure Device Identifier standard; is one of the founding members of the prpl Foundation and co-chair of its Security Engineering Group; and chairs the EEMBC IoT security benchmark working group. He holds a master’s degree in engineering from McMaster University in Ontario, Canada.   


Fergus Casey is a senior R&D manager for ARC Processors at Synopsys, with engineering responsibility for the ARC EM, ARC 600 and ARC 700 families. He joined ARC International in 2003 as a processor verification engineer and has worked in various roles within the ARC processor group as part of ARC International and through the acquisitions by Virage Logic and later Synopsys. Prior to joining ARC, Fergus worked in a number of fabless semi and IP companies and startups in Ireland and UK, including Toucan Technologies, PMC-Sierra and Icera. Fergus holds a bachelor’s degree in electrical engineering from University College Cork, Ireland.   


Rich Collins is the product marketing manager for IP subsystems at Synopsys and is responsible for developing strategies and positioning for market penetration and growth of ARC processors and ARC-based subsystems. Rich has over 20 years of experience in embedded semiconductor R&D, product marketing and business development. Before joining Synopsys, he spent 17 years at Motorola/Freescale, where he held several technical and managerial roles within CPU, IP and SoC design and marketing teams across the company. Rich holds an MBA from Duke University’s Fuqua School of Business and a BSE in Electrical Engineering from Duke University.   


Ruud Derwig has 20+ years of experience with software and system architectures for embedded systems. Key areas of expertise include (real-time, multi-core) operating systems, media processing, component based architectures, and security. He holds a master’s degree in computing science and a Ph.D. in engineering from Eindhoven University of Technology, the Netherlands. Ruud started his career at Philips Corporate Research, worked as a software technology competence manager at NXP Semiconductors, and is currently a software and systems architect at Synopsys.   


Linley Gwennap is the president of The Linley Group and principal analyst for mobile. One of the most respected analysts in the microprocessor industry, he has followed the industry for more than 20 years. Starting as a processor designer at Hewlett-Packard, Linley later worked in PA-RISC marketing and then became editor-in-chief of Microprocessor Report and vice president of MicroDesign Resources before founding The Linley Group in 1999.   


Kashif Kahn is the CEO and co-founder of Sage Senses, a Machine Learning startup specializing in Embedded Solutions for IoT applications. He is a serial entrepreneur and has deep expertise in Artificial Intelligence technologies in a variety of domains, including Natural Language Understanding. He takes a keen interest in sophisticated embedded machine learning solutions that can be deployed on low-power, small footprint microcontrollers for semantic interpretation of sensory data and that also significantly reduce 3rd party developers’ time, cost, and efforts for building sensory applications. Mr. Kahn is a graduate of the University of Pennsylvania and received a BSE in Computer Science from the Moore School and a BS in Economics from the Wharton School.   


Kulbhushan Kalra is an engineering manager for hardware development of ARC Processors at Synopsys. He is responsible for the development of advanced ARC processors including architecture, RTL design, verification and physical design. He joined Synopsys through the acquisition of Virage Logic. Prior to joining Virage Logic, he was managing the development of TriMedia DSP processors and MIPS processors at NXP Semiconductors for 12 years. Kulbhushan obtained his B.S. in Electronics and Communications Engineering from Delhi College of Engineering, India. His interests include computer architecture and multi-core high performance processors.   


Dave Karlin is the senior vice president of product strategy at Hillcrest Laboratories. He has over 35 years of experience in product development and strategic marketing, having held numerous R&D and marketing positions with Hewlett Packard and Agilent Technologies before joining Hillcrest Labs. Dave received his bachelor’s degree in electrical engineering from Cornell University, and as a Hewlett-Packard Fellow, he was awarded a master’s degree in electrical engineering from Stanford University.   


A. G. Karunakaran has 25 years of experience in general management, engineering and marketing for the computing, semiconductor and embedded markets. AGK was the founding president and CEO of GDA Technologies Inc., a leading Intellectual Property licensing and electronics design services company, which was acquired by L & T Infotech, India. At GDA, he was responsible for leadership development, growth strategy, prudent cash management and worked with leading semiconductor companies to commercialize the silicon intellectual property blocks. Under his leadership, GDA saw significant growth and became a leading supplier of High-speed Serial I/O Semiconductor Intellectual blocks.   


Seema Mirchandaney, engineering manager of software tools at Synopsys, is responsible for the development of compilers for the embedded vision processor. Prior to this she was technical director of software tools at On Demand Microelectronics and software architect at Cradle Technologies. Her research interests include compilers and parallel computation. She has published extensively in this area and has multiple patents in compiler algorithms. Seema obtained her MS from the University of Massachusetts, Amherst and BA in computer science from Smith College.   


Hugh O’Keeffe is Engineering Director with Ashling and has over 25 years’ experience in embedded systems and managing teams developing hardware and software debug tools. He has both a Bachelor of Engineering (Electronics) and Masters in Engineering (Computer & Communications Systems) from the University of Limerick, Ireland.   


Steve Ridley is an experienced hands-on engineer with 30 years’ knowledge of real time embedded systems, both as a hardware and software engineer. Steve has worked in the Automotive, Defence, Aerospace, Telecom, and Medical sectors and has an appreciation of both common and sector specific challenges facing embedded engineers in the industry. Steve is the lead engineer for WITTENSTEIN High Integrity Systems, the company behind SAFERTOS.   


Mitesh Shah is an engineering manager software development and simulation tools for ARC Processors at Synopsys. He joined Synopsys through the acquisition of Virage Logic. Earlier, he developed compilers and other related software development tools for a variety of processors such as Intel network processor, PowerPC, MIPS, and x86 at Teja Technologies, Mentor Graphics and Intel. Mitesh obtained his M.S. in computer science from Texas A&M University, College Station. His research interests include parallelizing compilers, multi-core software development, computer architecture and simulation.   

Kate Stewart is a Senior Director of Strategic Programs at the Linux Foundation responsible for the Zephyr Projects. With almost 30 years of experience in the software industry, she has held a variety of roles and worked as a developer in Canada, Australia and the US and for the last 20 years has managed software development teams, and product delivery, in the US, Canada, UK, India and China. She received her Master’s degree in Computer Science from University of Waterloo, and Bachelors of Computer Science (co-op program) from the University of Manitoba.   


Neil Trevett By day, Neil works at NVIDIA where he helps to drive the developer ecosystem that enables applications to take advantage of advanced silicon acceleration, with a particular focus on Augmented Reality. By night, Neil is the elected President of the Khronos Group industry standards consortium where he initiated the OpenGL ES standard now used by billions worldwide every day, helped catalyze the WebGL project to bring interactive 3D graphics to the Web, chairs the OpenCL working group defining the open standard for heterogeneous parallel computation and has helped establish and launch the new generation Vulkan API.   


Pim Tuyls is the Founder and CEO of Intrinsic-ID. He initiated the work on Physically Unclonable Functions (PUFs) that forms the basis of Intrinsic-ID’s silicon fingerprinting technology. The original work on PUFs was carried out at Phillips Research, where Pim was Principal Scientist and managed the cryptography cluster. In 2008 he founded Intrinsic-ID and led the technology development. Pim has headed the company since 2010 and raised new funding in 2012 to address the growing market of mobile and IoT security. In 2015 he moved the headquarters from the Netherlands to Silicon Valley. Pim Tuyls has a Ph.D. in mathematical physics from Leuven University, holds 50+ patents and is widely accepted for his work in the field of PUFs and security for embedded applications.


Vangelis Vassalos holds a B.Sc. degree in Physics Science, M.Sc. degree in Electronics and Computer Science and a Ph.D. in the area of Computer Arithmetic Circuit Design, from the Physics Department at the University of Patras. He is currently a software engineer at Irida Labs, developing cutting-edge embedded vision software optimized for market-leading applications.   


Bo Wu is a corporate applications engineer at Synopsys supporting the DesignWare EV vision processors. He holds Bachelors and Masters degrees from Tsinghua University in China, and a Ph.D. from University of Victoria in Canada. Between 1996 and 2000, he worked as a senior system engineer and DSP engineer at Nortel Networks in Ottawa and at AT&T Wireless in Seattle, respectively. Afterwards, he held various engineering and technical marketing positions focusing on system-level design products and processor solutions at Cadence, CoWare, and Synopsys.  


Uzi Zangi is a semiconductor industry veteran with over 22 years of experience in managing engineering teams, business and product lines in multi-disciplinary, global organizations, including Zoran Corporation and Siverge Networks. Uzi has experience in business development as Product Line General Manager in the consumer electronics market and as VP R&D in the Telecom market. He has managed the development of key technologies and multiple projects from concept to customer mass production. Uzi's strength is business management as well as complex technical project management of multi discipline R&D, Application, Marketing and Sales teams. He is co-founder and CEO of PLSense.